XRT72L56 Datasheet, PDF (23/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
PIN DESCRIPTION FOR THE XRT72L56
PIN #
A9
A10
A11
A12
A13
PIN NAME
RxFrame[0]
RxNib2[0]/
RxHDLCDat2[0]
RxOHFrame[0]/
RxHDLCDat4[0]
TxNibFrame[0]/
ValFCS[0]
TxOHClk[0]
TYPE
O
O
O
O
O
DESCRIPTION
Start of DS3/E3 Frame Indicator:
Functionality of this pin depends on whether the Framer is configured in
“Serial” or “nibble-parallel” mode.
Serial Mode Operation:
The Receive Section of the XRT72L56 will pulse this output pin “high” (for
one bit-period) when the “Receive Payload Data Output Interface” block is
driving the very first bit of a given DS3 or E3 frame, onto the “RxSer” output
pin.
Nibble-Parallel Operation:
The Receive Section of the XRT72L56 will pulse this output pin “high” (for
one nibble-period), when the “Receive Payload Data Output Interface” block
is driving the very first nibble of a given DS3 or E3 frame, onto the
“RxNib[3:0] output pins.
Receive Nibble Output - Channel 0, bit 2:
The Framer output "Received data (from the Remote Terminal) to the local
Terminal Equipment via this pin along with bits 1,3 and 4.
The data at this pin is updated on the rising edge of the RxClk output signal.
NOTE: This output pin is active only if the Nibble-Parallel Mode has been
selected.
Receive HDLC Data Output - Channel 0, bit 2:
This pin contains bit 2 RxHDLC data when the HDLC controller is turned on.
Receive Overhead Frame Boundary Indicator:- Channel 1
This output pin pulses "high" whenever the Receive Overhead Data
Output Interface” block outputs the first overhead bit (or nibble) of a
new DS3 or E3 frame.
Receive HDLC Data Output -Channel0, bit 4:
This pin contains bit 4 RxHDLC data when the HDLC controller is turned on.
Transmit Frame Boundary Indicator - Nibble/Parallel Interface:
This output pin pulses "high" when the last nibble of a given DS3 or E3
frame is expected at the TxNib[3:0] input pins.
The purpose of this output pin is to alert the Terminal Equipment that it
needs to begin transmission of a new DS3 or E3 frame.
Valid Frame Check Sequence:
When the HDLC is on, this pin will go high at the end of a valid Frame
Check Sequence.
Transmit Overhead Clock:
This output signal serves two purposes:
1. The Transmit Overhead Data Input Interface block will provide a rising
clock edge on this signal, one bit-period prior to the start to the instant that
the “Transmit Overhead Data Input Interface” block is processing an over-
head bit.
2. The Transmit Overhead Data Input Interface will sample the data at the
“TxOH” input pin, on the falling edge of this clock signal (provided that the
“TxOHIns” input pin is “HIGH”).
NOTE: The Transmit Overhead Data Input Interface block will supply a clock
edge for all overhead bits within the DS3 or E3 frame (via the “TxOHClk”
output signal). This includes those overhead bits that the “Transmit Over-
head Data Input Interface” will not accept from the Terminal Equipment.
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