XRT72L56 Datasheet, PDF (310/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
TXASOURCESEL[1:0]
SOURCE OF A BIT
00
TxE3 Service Bits Register (Address = 0x35)
01
Transmit Overhead Data Input Interface
10
Transmit Payload Data Input Interface
11
Functions as a FEBE (Far-End-Block Error) bit-field.
This bit-field is set to "0", if the Near-End Receive Section (within this chip) detects no BIP-4
Errors within the incoming E3 frames.
This bit-field is set to "1", if the Near-End Receive Section (within this chip) detects a BIP-4
Error within the incoming E3 frame.
Hence, if a Yellow Alarm condition needs to be trans-
mitted to the Remote Terminal Equipment, this can
be accomplished by executing the following steps.
STEP 1 - Write a “1” into Bit 1 (A Bit) within the Tx
E3 Service Bits Register, as indicated below.
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
A Bit
N Bit
RO
RO
RO
RO
RO
RO
R/W
R/W
0
0
0
0
0
0
1
0
STEP 2 - Write the value “00” into the TxAS-
ource[1:0] bit-fields within the Tx E3 Configura-
tion Register, as indicated below.
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Tx BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
R/W
R/W
R/W
R/W
R/W
X
0
0
X
X
BIT 2
Tx AIS
Enable
R/W
X
BIT 1
Tx LOS
Enable
R/W
X
BIT 0
Tx FAS
Source Select
R/W
X
These two steps will cause the Transmit E3 Framer
block to read in the contents of Bit 1 (within the Tx E3
Service Bit register) and insert it into the “A” bit-field
within the outbound E3 data stream. Hence, the “A”
bit will be set to “1”, which will be interpreted as an
Alarm Condition, by the Remote Terminal Equipment.
5.2.4.2.2 Configuring the Transmit E3 Framer
block to insert the BIP-4 nibble into each out-
bound E3 frame.
The XRT72L56 Framer IC permits the user to (1) con-
figure the Transmit Section of the device to insert the
BIP-4 value into each outbound E3 frame and (2) to
configure the Receive Section of the device to com-
pute and verify the BIP-4 value, within each inbound’
E3 frame.
These two configurations are accomplished by setting
bit 7 (Tx BIP-4 Enable), within the Tx E3 Configura-
tion Register, to “1”, as indicated below.
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