XRT72L56 Datasheet, PDF (333/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
• Asserting the RxLOS output pin (e.g., toggling it
"High”).
• Setting Bit 4 (RxLOS) of the Rx E3 Configuration &
Status Register to “1” as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
R/W
RO
RO
RO
RO
RO
RO
0
1
1
1
0
0
0
BIT 0
RxFERF
RO
0
• The Receive E3 Framer block will generate a
Change in LOS Condition interrupt request. Upon
generating this interrupt request, the Receive E3
Framer block will assert Bit 1 (LOS Interrupt Status
within the Rx E3 Framer Interrupt Status Register -
1, as depicted below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
RO
RO
RO
RUR
RUR
0
0
0
0
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
1
BIT 0
AIS
Interrupt
Status
RUR
0
Clearing the LOS Condition
The Receive E3 Framer block will clear the LOS con-
dition when it encounters a stream of 32 bits that
does not contain a string of 4 consecutive zeros.
When the Receive E3 Framer block clears the LOS
condition, then it will notify the Microprocessor and
the external circuitry of this occurrence by:
• Generating the Change in LOS Condition Interrupt
to the Microprocessor.
• Clearing Bit 4 (RxLOS) within the Rx E3 Configura-
tion & Status Register, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
0
0
1
1
1
• Clear the RxLOS output pin (e.g., toggle it "Low”).
5.3.2.8 The AIS (Alarm Indication Status) Con-
dition
Declaring the AIS Condition
The Receive E3 Framer block will identify and declare
an AIS condition, if it detects an All Ones” pattern in
the incoming E3 data stream. More specifically, the
Receive E3 Framer block will declare an AIS Condi-
tion if 7 or less “0’s” are detected in each of 2 consec-
utive E3 frames.
If the Receive E3 Framer block declares an AIS Con-
dition, then it will do the following.
• Generate the Change in AIS Condition Interrupt to
the Microprocessor. Hence, the Receive E3
Framer block will assert Bit 0 (AIS Interrupt Status)
within the Rx E3 Framer Interrupt Status register -
1, as depicted below.
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