XRT72L56 Datasheet, PDF (431/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
Interrupt Status Register - 1, will be set to “1”, as de-
picted below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
RO
RO
RO
RUR
RUR
0
0
0
0
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
0
The Receive E3 Framer block will also inform the ex-
ternal circuitry of its transition into the OOF Condition
state, by toggling the RxOOF output pin “High”.
If the Receive E3 Framer block is capable of finding
the Framing Alignment octets within a user-selectable
number of E3 frame periods, then it will transition
back into the In-Frame state. The Receive E3 Framer
block will then inform the Microprocessor/Microcon-
troller of its transition back into the In-Frame state by
generating the Change in OOF Condition Interrupt.
However, if the Receive E3 Framer block resides in
the OOF Condition state for more than this user-se-
lectable number of E3 frame periods, then it will auto-
matically transition to the LOF (Loss of Frame) Condi-
tion state.
The user can select this user-selectable number of
E3 frame periods that the Receive E3 Framer block
will remain in the OOF Condition state by writing the
appropriate value into Bit 7 (RxLOF Algo) within the
Rx E3 Configuration & Status Register, as depicted
below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS RxPld Unstab
R/W
RO
RO
RO
RO
RO
0
1
1
1
1
1
BIT 1
Rx
TMark
RO
1
BIT 0
RxFERF
RO
1
Writing a “0” into this bit-field causes the Receive E3
Framer block to reside in the OOF Condition state for
at most 24 E3 frame periods (3 ms). Writing a “1” into
this bit-field causes the Receive E3 Framer block to
reside in the OOF Condition state for at most 8 E3
frame periods (1 ms).
LOF (Loss of Framing) Condition State
If the Receive E3 Framer block enters the LOF Condi-
tion state, then the following things will happen.
• The Receive E3 Framer block will discard the most
recent frame synchronization and
• The Receive E3 Framer block will make an uncon-
ditional transition to the FA1, FA2 Octet Search
state.
• The Receive E3 Framer block will notify the Micro-
processor/Microcontroller of its transition to the
LOF Condition state, by generating the Change in
LOF Condition interrupt. When this occurs, Bit 2
(LOF Interrupt Status), within the Rx E3 Interrupt
Status Register - 1 will be set to “1”, as depicted
below.
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