XRT72L56 Datasheet, PDF (104/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
2.4.3.4 3.3.2.18 Receive E3 Interrupt Enable
Register - 2 (E3, ITU-T G.832)
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TTB
Change
Interrupt
Enable
Not Used
FEBE
Interrupt
Enable
FERF
Interrupt
Enable
BIP-8
Error Interrupt
Enable
Framing
Byte Error
Interrupt
Enable
RxPld
Mis
Interrupt
Enable
RO
R/W
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 6 - TTB Change Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in Trail Trace Buffer Message in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on Trail Trace Buffer mes-
sages, please see Section 5.3.2.9.
Bit 5 - Received LAPD Message Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Received LAPD Message frame interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 5.3.6.1.12.
Bit 4 - FEBE (Far-End Block Error) Interrupt En-
able
This Read/Write bit-field allows the user to enable or
disable the Far-End-Block Error (FEBE) interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
NOTE: For more information on the FEBE Interrupt condi-
tion, please see Section 5.3.6.1.8.
Bit 3 - FERF (Far-End Receive Failure) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in FERF Condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the Change in FERF Condi-
tion interrupt, please see Section 5.3.6.1.7.
Bit 2 - EM Byte Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the EM Byte Error interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 5.3.6.1.9.
Bit 1 - Framing Byte Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Framing Byte Error interrupt. Setting this
bit-field to "1" enables this interrupt. Setting this bit-
field to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 5.3.6.1.10.
Bit 0 - Receive Payload Type Mismatch Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Receive Payload Type Mismatch interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 5.3.6.1.11.
2.4.3.5 Receive E3 Interrupt Status Register -
1 (E3, ITU-T G.832)
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
Not Used
BIT 6
SSM MSG
Interrupt
Status
BIT 5
SSM OOS
Interrupt
Status
BIT 4
COFA
Interrupt
Status
BIT 3
OOF
Interrupt
Status
BIT 2
LOF
Interrupt
Status
BIT 1
LOS
Interrupt
Status
BIT 0
AIS
Interrupt
Status
RO
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
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