XRT72L56 Datasheet, PDF (223/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
4.3.1.2.1 AMI Decoding
AMI or Alternate Mark Inversion, means that consec-
utive one's pulses (or marks) will be of opposite polar-
ity with respect to each other. This line code involves
the use of three different amplitude levels: +1, 0, and -
1. The +1 and -1 amplitude signals are used to repre-
sent one's (or mark) pulses and the "0" amplitude
pulses (or the absence of a pulse) are used to repre-
sent zeros (or space) pulses. The general rule for the
AMI line code is: if a given mark pulse is of positive
polarity, then the very next mark pulse will be of nega-
tive polarity and vice versa. This alternating-polarity
relationship exists between two consecutive mark
pulses, independent of the number of zeros that exist
between these two pulses. Figure 76 presents an il-
lustration of the AMI Line Code as would appear at
the RxPOS and RxNEG input pins of the Framer, as
well as the corresponding output signal on the line.
FIGURE 76. ILLUSTRATION OF AMI LINE CODE
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
Line Signal
RxPOS
RxNEG
NOTE: One of the reasons that the AMI Line Code has
been chosen for driving copper medium, isolated via trans-
formers, is that this line code has no dc component, thereby
eliminating dc distortion in the line.
4.3.1.2.2 B3ZS Decoding
The Transmit DS3 LIU Interface block and the associ-
ated LIU embed and combine the data and clocking
information into the line signal that is transmitted to
the remote terminal equipment. The remote terminal
equipment has the task of recovering this data and
timing information from the incoming DS3 data
stream. Most clock and data recovery schemes rely
on the use of Phase-Locked-Loop technology. One of
the problems of using Phase-Locked-Loop (PLL)
technology for clock recovery is that it relies on transi-
tions in the line signal, in order to maintain lock with
the incoming DS3 data-stream. Therefore, these
clock recovery scheme, are vulnerable to the occur-
rence of a long stream of consecutive zeros (e.g., no
transitions in the line). This scenario can cause the
PLL to lose lock with the incoming DS3 data, thereby
causing the clock and data recovery process of the
receiver to fail. Therefore, some approach is needed
to insure that such a long string of consecutive zeros
can never happen. One such technique is B3ZS (or
Bipolar 3 Zero Substitution) encoding.
In general the B3ZS line code behaves just like AMI
with the exception of the case when a long string of
consecutive zeros occurs on the line. Any 3 consecu-
tive zeros will be replaced with either a 00V or a B0V
where B refers to a Bipolar pulse (e.g., a pulse with a
polarity that is compliant with the alternating polarity
scheme of the AMI coding rule). And V refers to a Bi-
polar Violation pulse (e.g., a pulse with a polarity that
violates the alternating polarity scheme of AMI.) The
decision between inserting an 00V or a B0V is made
to insure that an odd number of Bipolar (B) pulses ex-
ist between any two Bipolar Violation (V) pulses. The
Receive DS3 Framer, when operating with the B3ZS
Line Code is responsible for decoding the B3ZS-en-
coded data back into a unipolar (binary-format). For
instance, if the Receive DS3 Framer detects a 00V or
a B0V pattern in the incoming pattern, the Receive
DS3 Framer will replace it with three consecutive ze-
ros. Figure 77 presents a timing diagram that illus-
trates examples of B3ZS decoding.
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