XRT72L56 Datasheet, PDF (20/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................ 428
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 428
Figure 201. Flow Chart depicting the Functionality of the LAPD Receiver ......................................... 429
Figure 202. Flow Chart depicting the Functionality of the LAPD Receiver (Continued) ..................... 430
6.3.4 The Receive Overhead Data Output Interface ...................................................................................... 430
Figure 203. A Simple Illustration of the Receive Overhead Output Interface block ............................ 430
Figure 204. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 1). ............................................................................................................. 431
TABLE 88: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ................................................................................................................................. 432
TABLE 89: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-
HFRAME WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT
PIN ........................................................................................................................................................ 432
Figure 205. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method
1). ........................................................................................................................................................ 434
TABLE 90: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2) ............................................................................................................. 435
Figure 206. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 2). ............................................................................................................. 436
TABLE 91: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME
WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ...
436
Figure 207. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 439
6.3.5 The Receive Payload Data Output Interface ......................................................................................... 439
Figure 208. A Simple illustration of the Receive Payload Data Output Interface block ...................... 440
TABLE 92: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK .................................................................................................................................... 441
Figure 209. Illustration of the Receive Payload Data Output Interface Block (of the XRT72L56 DS3/E3
Framer IC) being interfaced to the Receive Terminal Equipment (Serial Mode Operation) ................ 442
Figure 210. An Illustration of the behavior of the signals between the Receive Payload Data Output Inter-
face block of the XRT72L56 and the Terminal Equipment .................................................................. 443
Figure 211. Illustration of the XRT72L56 DS3/E3 Framer IC being interfaced to the Receive Section of the
Terminal Equipment (Nibble-Mode Operation) .................................................................................... 444
Figure 212. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 445
6.3.6 Receive Section Interrupt Processing ................................................................................................... 445
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ...................................................................... 446
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 446
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 447
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ......................................................... 447
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 448
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 448
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ......................................................... 448
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 449
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ......................................................... 449
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................ 450
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 450
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 450
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 451
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ......................................................... 451
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 451
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 452
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 452
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 453
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