XRT72L56 Datasheet, PDF (476/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
DL from NR
BIT 2
RxLAPD
Enable
R/W
R/W
0
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
0
BIT 0
RxLAPD
Interrupt
Status
RUR
X
Writing a “1” into this bit-field enables the Receive
LAPD Message Interrupt. Conversely, writing a “0”
into this bit-field disables the Receive LAPD Message
Interrupt.
Servicing the Receive LAPD Message Interrupt
Whenever the XRT72L56 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “Low”.
• It will set Bit 0 (RxLAPD Interrupt Status), within the
Rx E3 LAPD Control register to “1”, as indicated
below.
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
DL from NR
BIT 2
RxLAPD
Enable
R/W
R/W
0
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
1
BIT 0
RxLAPD
Interrupt
Status
RUR
1
• It will write the contents of the newly Received
LAPD Message into the Receive LAPD Message
buffer (located at 0xDE through 0x135).
Whenever the Terminal Equipment encounters the
Receive LAPD Message Interrupt, then it should read
out the contents of the Receive LAPD Message buff-
er, and respond accordingly.
457