XRT72L56 Datasheet, PDF (183/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
4.2.1.5 Mode 5 - The Nibble-Parallel/Local-
Timed/Frame-Slave Interface Mode Behavior of
the XRT72L56
If the XRT72L56 has been configured to operate in
this mode, then the XRT72L56 will function as fol-
lows:
A. Local-Timed (Uses the TxInClk signal as the
Timing Reference)
In this mode, the Transmit Section of the XRT72L56
will use the TxInClk signal at its timing reference.
Further, the chip will internally divide the TxInClk
clock signal by a factor of 4 and will output this divid-
ed clock signal via the TxNibClk output pin. The
Transmit Terminal Equipment Input Interface block
(within the XRT72L56) will use the rising edge of the
TxNibClk signal, to latch the data, residing on the Tx-
Nib[3:0] into its circuitry.
B. Nibble-Parallel Mode
The XRT72L56 will accept the DS3 payload data,
from the Terminal Equipment, in a parallel manner,
via the TxNib[3:0] input pins. The Transmit Terminal
Equipment Input Interface will latch this data into its
circuitry, on the rising edge of the TxNibClk output
signal.
C. Delineation of outbound DS3 Frames
The Transmit Section will use the TxInClk input signal
as its timing reference and will use the TxFrameRef
input signal as its Framing Reference (e.g., the Trans-
mit Section of the XRT72L56 initiates frame genera-
tion upon the rising edge of the TxFrameRef signal).
NOTE: In this case, the Terminal Equipment should pulse
the TxFrameRef input signal (of the XRT72L56 Framer IC)
coincident with it applying the first payload nibble, within a
given outbound DS3 frame. Hence, the duration of this
pulse should be one nibble-period of the DS3 signal (see
Figure 53).
D. Sampling of payload data, from the Terminal
Equipment
In Mode 5, the XRT72L56 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNibClk
signal (see Figure 53).
NOTE: The TxNibClk signal, from the XRT72L56 operates
nominally at 11.184 MHz (e.g., 44.736 MHz divided by 4).
However, for reasons described below, TxNibClk effectively
operates at a "Low"er clock frequency. The Transmit Pay-
load Data Input Interface is only used to accept the payload
data, which is intended to be carried by outbound DS3
frames. The Transmit Payload Data Input Interface is not
designed to accommodate the entire DS3 data stream.
The DS3 Frame consists of 4704 payload bits or 1176
nibbles. Therefore, the XRT72L56 will supply 1176
TxNibClk pulses between the rising edges of two con-
secutive TxNibFrame pulses. The DS3 Frame repeti-
tion rate is 9.398kHz. Hence, 1176 TxNibClk pulses
for each DS3 frame period amounts to TxNibClk run-
ning at approximately 11.052 MHz. The method by
which the 1176 TxNibClk pulses are distributed
throughout the DS3 frame period is presented below.
Nominally, the Transmit Section within the XRT72L56
will generate a TxNibClk pulse for every 4 RxOutClk
(or TxInClk) periods. However, in 14 cases (within a
DS3 frame period), the Transmit Payload Data Input
Interface will allow 5 TxInClk periods to occur be-
tween two consecutive TxNibClk pulses.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L56 to the Terminal Equip-
ment for Mode 5 Operation
Figure 52 presents an illustration of the Transmit Pay-
load Data Input Interface block (within the XRT72L56)
being interfaced to the Terminal Equipment, for Mode
5 Operation.
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