XRT72L56 Datasheet, PDF (201/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
all 1s in the FEAC bit-field of each DS3 Frame. The
Receive FEAC Processor (at the remote terminal
equipment) will interpret this all 1s message as an
Idle FEAC Message. The Transmit FEAC Processor
will continue sending all 1s in the FEAC bit field, for
an indefinite period of time, until the local µP/µC com-
mands it to transmit a new FEAC message.
Figure 61 presents a flow chart depicting how to use
the Transmit FEAC Processor.
FIGURE 61. A FLOW CHART DEPICTING HOW TO TRANSMIT A FEAC MESSAGE VIA THE FEAC TRANSMITTER
SSTTAARRTT
11
WWRRITITEESSIXIX-B-BITIT“O“OUUTTBBOOUUNNDD””FFEEAACCVVAALLUUEE
ININTTOOTTHHEETTxDxDSS33FFEEAACCRRegegisitsetrer
TThihsisrergegisitsetrerisislolcoactaetdedatatAAdddrdersesss0x03x23.2.
EENNAABBLLEETTHHEETTRRAANNSSMMITITFFEEAACCPPRROOCCEESSSSOORR. _.
TThihsisisisacaccocmomplpilsihshededbbyywwrirtiitnigng“x“xxxxxxxx1xx1xx”x”
initnotothteheTTxDxDSS33FFEEAACCCConofnifgiguruartaitoinon&&SStattautsusRRegeigsitsetrer
ININITITIAIATTEETTRRAANNSSMMISISSSIOIONNOOFFTTHHEE“O“OUUTTBBOOUUNNDD””
FFEEAACCMMEESSSSAAGGEE. _.
TThhisisisisacaccocommpplilsihshededbbyywwrirtiitningg“x“xxxxxxxxxxx11xx””inintotoththee
TTxxDDSS33FFEEAACCCCoonnfifgiguurartaitoionn&&SStattautus _{sRRegegisitsetre.r.}
TTRRAANNSSMMITITFFEEAACCPPRROOCCEESSSSOORRPPRROOCCEEEEDDSSTTOO
ININSSEERRTTTTHHEE161-6B-BITITMMEESSSSAAGGEE(I(NINAABBITIT-B-BYY-B-BITIT
MMAANNNNEERR) _{)ININTTOOTTHHEE“F“FEEAACC””BBITIT-F-FIEIELLDDSSOOFF}
EEAACCHHOOUUTTBBOOUUNNDDDDSS33FFRRAAMMEE. _.
HHasas
NO
ththee1166-b-bitit
FFEEAACCMMesessasgaegebebeenen
trtarnasnmsmitittetdedtotoththee
RRememotoeteTTeremrmininalal
1100titmimeses
??
YES
IsIs
TTrarnansmsmisissisoionn
oof _{fththee1166BBititFFEEAACC}
MMesessasgagee
CCoommpplelteete
??
YES
NO
GGEENNEERRAATTEETTHHEETTRRAANNSSMMITITFFEEAACC
ININTTEERRRRUUPPTT
TTRRAANNSSMMITITFFEEAACCPPRROOCCEESSSSOORREENNCCAAPPSSUULLAATTEESS
TTHHEE“O“OUUTTBBOOUUNNDD””FFEEAACCVVAALLUUEEININTTOOAA1616BBITIT
FFRRAAMMININGGSSTTRRUUCCTTUURREE. _.
ININVVOOKKEETTHHEE“T“TRRAANNSSMMITITFFEEAACCININTTEERRRRUUPPTT
SSEERRVVICICEERROOUUTTININEE. _.
11
For a detailed description of the Receive FEAC Pro-
cessor (within the Receive DS3 HDLC Controller
block), please see Section 3.3.3.1.
4.2.3.2 Message-Oriented Signaling (e.g.,
LAP-D) processing via the Transmit DS3 HDLC
Controller
The LAPD Transmitter (within the Transmit DS3
HDLC Controller Block) allows the user to transmit
path maintenance data link (PMDL) messages to the
remote terminal via the outbound DS3 Frames. In
this case the message bits are inserted into and car-
ried by the 3 DL bit fields of F-Frame #5 within each
DS3 M-frame. The on-chip LAPD transmitter sup-
ports both the 76 byte and 82 byte length message
formats, and the Framer IC allocates 88 bytes of on-
chip RAM (e.g., the Transmit LAPD Message buffer)
to store the message to be transmitted. The mes-
sage format complies with ITU-T Q.921 (LAP-D) pro-
tocol with different addresses and is presented below
in Figure 62.
182