XRT72L56 Datasheet, PDF (473/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
1
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error Interrupt
Status
RUR
0
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters the
Detection of FEBE Event Interrupt, it should do the
following.
• It should read the contents of the PMON FEBE
Event Count Registers (located at Addresses 0x56
and 0x57) in order to determine the number of
FEBE Events that have been received by the
XRT72L56 Framer IC.
6.3.6.2.9 The Detection of BIP-8 Error Interrupt
If the Detection of BIP-8 Error Interrupt is enabled,
then the XRT72L56 Framer IC will generate an inter-
rupt, anytime the Receive E3 Framer block has de-
tected an error in the EM (Error Monitoring) byte,
within an incoming E3 frame.
Enabling and Disabling the Detection of FEBE
Event Interrupt
The user can enable or disable the Detection of BIP-8
Error’ interrupt by writing the appropriate value into
Bit 2 (BIP-8 Interrupt Enable) within the Rx E3 Inter-
rupt Enable Register - 2, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
X
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error
Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Detection of the BIP-8 Error Inter-
rupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “High”.
• It will set the Bit 2 (BIP-8 Interrupt Status), within
the RxE3 Interrupt Status Register - 2 as indicated
below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error
Interrupt
Status
RUR
1
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters the
lowing.
Detection of BIP-8 Error Interrupt, it should do the fol-
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