XRT72L56 Datasheet, PDF (141/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
2.4.7.7 Transmit E3 BIP-4 Error Mask Register
(ITU-T G.751)
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
TxBIP-4 Mask[3:0]
R/W
R/W
0
0
XRT72L56
REV. P1.1.2
BIT 0
R/W
0
Bits 3 - 0: TxBIP-4 Mask[3:0]
This Read/Write bit-field permits the user to insert er-
rors into the BIP-4 value within each outbound E3
frame. The user may wish to do this for equipment
testing purposes. Prior to transmission, the Transmit
DS3/E3 Framer block reads in the BIP-4 value, and
performs an XOR operation with it and the contents of
this register. The results of this operation are written
back into the BIP-4 nibble position, in each outbound
E3 frame. Consequently, to insure errors are not in-
jected into the BIP-4 value of the outbound E3
frames, the contents of this register must be set to all
"0’s" (the default value).
NOTE: This register is ignored if Bit 7 (Tx BIP-4 Enable)
within the “TxE3 Configuration” register (Address = 0x30) is
set to “0”.
2.4.8 Performance Monitor Registers
2.4.8.1 PMON Line Code Violation Count Reg-
ister - MSB
PMON LCV EVENT COUNT REGISTER - MSB (ADDRESS = 0X50)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
LCV Event Count Register - LSB (Address = 0x51)
contains a 16-bit representation of the number of Line
Code Violations that have been detected by the Re-
ceive DS3/E3 Framer block, since the last read of
these registers. This register contains the MSB (or
Upper-Byte) value of this 16 bit expression.
2.4.8.2 PMON Line Code Violation Count Reg-
ister - LSB
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
LCV Event Count Register - LSB (Address = 0x50)
contains a 16-bit representation of the number of Line
Code Violations that have been detected by the Re-
ceive DS3/E3 Framer block, since the last read of
these registers. This register contains the LSB (or
Lower-Byte) value of this 16 bit expression.
2.4.8.3 PMON Framing Bit/Byte Error Count
Register - MSB
122