XRT72L56 Datasheet, PDF (154/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
ter, and is presented below for the sake of complete-
ness.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxDS3/E3
Interrupt
Status
Not Used
R/W
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RO
0
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PRELIMINARY
BIT 1
TxDS3/E3
Interrupt
Status
R/W
0
BIT 0
One-Second
Interrupt
Status
R/W
0
The Block Interrupt Enable register allows the user to
individually enable or disable the interrupt requesting
capability of the functional blocks, within the Framer
IC. If a particular bit-field, within this register contains
the value "0", then the corresponding functional block
has been disabled from generating any interrupt re-
quests. Conversely, if that bit-field contains the value
"1", then the corresponding functional block has been
enabled for interrupt generation (e.g., those potential
interrupts, within the enabled functional block that are
enabled at the source level, are now enabled). The
user should be aware of the fact that each functional
block, within the Framer IC contains anywhere from 1
to 12 potential interrupt sources. Each of these lower
level interrupt sources contain their own set of inter-
rupt enable bits and interrupt status bits, existing in
various on-chip registers.
Interrupt Service Routing Branching: after reading
the Block Interrupt Status Register.
The contents of the Block Interrupt Status Register
identify which of 3 functional blocks (within the Fram-
er IC) has requested interrupt service. The local µP
should use this information in order to determine
where, within the Interrupt Service Routing, program
control should branch to. Table 10 can be viewed as
an interrupt service routine guide. It lists each of the
Functional Blocks, that contain a bit-field in the Block
Interrupt Status Register. Additionally, this table also
presents a list and addresses of corresponding on-
chip Registers that the Interrupt Service Routine
should branch to and read, based upon the Interrupt-
ing Functional Block.
Table 10, Table 11, and Table 12 presents the Inter-
rupt Service Routine guide for DS3, E3/ITU-T G.832
and E3/ITU-T G.751 applications, respectively.
TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR DS3 APPLICATIONS)
INTERRUPTING
FUNCTIONAL BLOCK
THE NEXT REGISTERS TO BE READ DURING THE INTERRUPT SERVICE
ROUTINE
REGISTER ADDRESS
Receive Section RxDS3 Interrupt Status Register
0 x 013
RxDS3 FEAC Interrupt Enable/Status Register
0 x 17
RxDS3 LAPD Control Register
0 x 18
Transmit Section TxDS3 FEAC Configuration and Status Register
0 x 31
TxDS3 LAPD Status/Interrupt Register
0 x 34
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