XRT72L56 Datasheet, PDF (229/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
TABLE 39: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3
CONFIGURATION AND STATUS REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE
RECEIVE DS3 FRAMER BLOCK
F-SYNC ALGO (BIT 1)
0
1
OOF DECLARATION CRITERIA
OOF is declared when 6 out of 16 consecutive F-bits are in error.
OOF is declared when 3 out of 16 consecutive F-bits are in error.
NOTE: Once the Receive DS3 Framer block has declared
an OOF condition, it will transition back to the F-Bit Search
state within the DS3 Frame Acquisition/Maintenance algo-
rithm (per Figure 81).
In addition to selecting an OOF Declaration criteria
for the F-bits, the user has the following options for
configuring the OOF Declaration criteria based upon
M-bits.
1. M-bit errors do not cause a OOF Declaration, or
2. OOF will be declared if 3 out of 4 consecutive M-
bits are in error.
The user will select between these two options by
writing the appropriate value to Bit 0 (M-Sync Algo)
within the Receive DS3 Configuration and Status
Register, as depicted below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
RxAIS
BIT 6
RxLOS
BIT 5
RxIdle
BIT 4
RxOOF
RO
RO
RO
RO
X
X
X
X
Table 40 relates the contents of this Bit Field to the M-
Bit Error criteria for Declaration of OOF.
BIT 3
Int LOS
Disable
R/W
X
BIT2
Framing on
Parity
R/W
X
BIT 1
BIT 0
F-Sync Algo M-Sync Algo
R/W
R/W
X
X
TABLE 40: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3
CONFIGURATION AND STATUS REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE
RECEIVE DS3 FRAMER BLOCK
MSYNC ALGO
0
1
OOF DECLARATION CRITERIA
M-Bit Errors do not result in the declaration of OOF
OOF is declared when 3 out of 4 M-bits are in error.
The Framing on Parity Criteria for OOF Declara-
tion
Finally, the Framer IC offers the Framing on Parity op-
tion, which also effects the OOF Declaration criteria.
As was mentioned earlier, the Framer IC allows the
user to configure the Receive DS3 Framer block to
detect 'valid-parity' before declaring itself In-Frame.
This same selection also configures the Receive DS3
Framer block to also declare an OOF Condition if a P-
bit error is detected in 2 of the last 5 M-frames.
Whenever the Receive DS3 Framer block declares
OOF after being in the In-Frame State the following
will happen.
• The Receive DS3 Framer will assert the RxOOF
output pin (e.g., toggles it "High").
• Bit 4 (RxOOF) within the Rx DS3 Configuration and
Status Register will be set to "1" as depicted below.
Rx DS3 Configuration and Status Register, (Address
= 0x10)
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
RxAIS
BIT 6
RxLOS
BIT 5
RxIdle
BIT 4
RxOOF
BIT 3
Int LOS
Disable
BIT2
Framing on
Parity
BIT 1
BIT 0
F-Sync Algo M-Sync Algo
210