XRT72L56 Datasheet, PDF (28/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
PIN DESCRIPTION FOR THE XRT72L56
PIN #
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
PIN NAME
TxNib3[
TxHDLCDat3[0]
RxLOS[5]
RxOHClk[5]/
RxHDLCClk[5]
RxNib1[5]/
RxHDLCDat1[5]
RxClk[5]
TxNibClk[5]/
SndFCS[5]
TxOHClk[5]
TxOHIns[5]/
TxHDLCDat4[5]
TxNib3[5]/
TxHDLCDat3[5]
RxNib0[2]/
RxHDLCDat0[2]
TYPE
I
O
O
DESCRIPTION
Transmit Nibble-Parallel Payload Data Input -Channel 0, bit 3:
See Description for pin A23.
Transmit HDLC Data Input :
This pin accepts bit 3 TxHDLC data when the HDLC controller is turned on.
See Description for Pin A8
See Description for Pin B10
O See Description for Pin A25
O See Description for Pin B9
O Transmit Nibble Clock Signal:
When the device is configured in Nibble Parallel mode, this clock
can be derived from either TxLnClk or Rx LnClk, (depending upon
which signal is selected as the timing reference).
The terminal equipment must be configured to output data to the Tx-
Nib[3:0] input pins on the rising edge of this clock signal.
NOTES:
1. For DS3 applications, the XRT72l56 will output 1176 clock edges
(to the Terminal Equipment) for each “outbound” DS3 frame.
2. For E3, ITU-T G.832 applications, the XRT72l56 will output 1074
clock edges (to the Terminal Equipment) for each “outbound” E3
frame.
3. For E3, ITU-T G.751 applications, the XRT72L56 will output 384
clock edges (fo the Terminal Equipment) for each “outbound” E3
frame.
Send FCS:
I
When the HDLC controller is turned on, this pin is driven “High” during the
time when FCS bytes are being sent after a valid HDLC message.
O See Description for Pin A13
I
See Description for Pin A16
I
See Description for Pin B15
O See Description for Pin A18
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