XRT72L56 Datasheet, PDF (413/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
NOTE: When this bit is set, it overrides all of the other bits in
this register.
6.2.4.2.1.3 TxMARx - Bit 0
This read/write bit-field permits the user to force the
XRT72L56 Framer IC to transmit either a FERF (Far-
End Receive Failure) or a FEBE (Far-End Block Er-
ror) indication to the remote terminal equipment.
6.2.4.2.2 Configuring the Transmit Trail Trace
Buffer Message
The XRT72L56 Framer IC contains 16 bytes worth of
Transmit Trail Trace Buffer registers and 16 bytes
worth of Receive Trail Trace Buffer registers. The role
of the Receive Trail Trace Buffer registers are de-
scribed in Section 5.3.7.
The XRT72L56 Framer IC contains 16 Transmit Trail
Trace Buffer registers (e.g., Tx TTB-0 through TxTTB-
15). The purpose of these registers are to provide a
16-byte Trail Access Point Identifier to the Remote
Terminal Equipment. The Remote Terminal Equip-
ment will use this information in order to verify that it
is still receiving data from its intended transmitter.
The specific use of these registers follows.
For Trail Trace Buffer Message purposes, the Trans-
mit E3 Framer block will group 16 consecutive E3
frames, into a Trail Trace Buffer super-frame. When
the Transmit E3 Framer block is generating the first
E3 frame, within a Trail Trace Buffer super-frame, it
will read in the contents of the Tx TTB-0 Register (Ad-
dress = 0x38) and insert this value into the “TR” byte-
field of this very first Outbound E3 frame. When the
Transmit E3 Framer is generating the very next E3
frame (e.g., the second E3 frame, within the Trail
Trace Buffer super-frame), it will read in the contents
of the Tx TTB-1 register (Address = 0x39) and insert
this value into the TR byte-field of this Outbound E3
frame. As the Transmit E3 Framer block is creating
each subsequent E3 frame, within this Trail Trace
Buffer super frame, it will continue to increment to the
very next Transmit Trail Trace Buffer register. The
Transmit E3 Framer block will then read in the con-
tents of this particular Transmit Trail Trace Buffer reg-
ister (Tx TTB-n) and insert this value into the TR byte-
field of the very next Outbound E3 frame. After the
Transmit E3 Framer block has created the 16th E3
frame, within a given Trail Trace Buffer super-frame
(e.g., it has read in the contents of Tx TTB-15 register
and has inserted this value into the “TR” byte of the
16th E3 frame), it will begin to create a new Trail Trace
Buffer super-frame, by reading the contents of the Tx
TTB-0 register, and repeating the above-mentioned
procedure.
The contents of the Tx TTB-0 register will typically be
of the form [1, C6, C5, C4, C3, C2, C1, C0]. The “1”
in the MSB (Most Significant bit) position of this byte
is used to designate that this octet is the frame-start
marker (e.g., is the first of the 16 TR bytes, within a
Trail Trace Buffer super-frame). The remaining Trail
Trace Buffer registers (TxTTB-1 through TxTTB-15)
will typically contain a “0” in their MSB positions. The
remaining bits within the Tx TTB-0 register C6
through C0 are the CRC-7 bits calculated over the
contents of all 16 TR bytes, within the previous Trail
Trace Buffer super-frame. The contents of the re-
maining Trail Trace Buffer registers (e.g., Tx TTB-1
through Tx TTB-15) will typically contain the 15 ASCII
characters required for the E.164 numbering format.
NOTES:
1. The XRT72L56 Framer IC will not compute the
CRC-7 value, to be written into the Tx TTB-0 regis-
ter. The user’s system must compute this value
prior to writing it into the Tx TTB-0 register.
2. The user, when writing data into the Tx TTB regis-
ters, must take care to insure that only the Tx TTB-
0 register contains an octet with a “1” in the MSB
(most significant bit) position. All remaining Tx TTB
registers (e.g., Tx TTB-1 through Tx TTB-15) must
contain octets with a “0” in the MSB position. The
reason for this cautionary note is presented in Sec-
tion 5.3.2.9.
6.2.5 The Transmit E3 Line Interface Block
The XRT72L56 Framer IC is a digital device that
takes E3 payload and overhead bit information from
some terminal equipment, processes this data and ul-
timately, multiplexes this information into a series of
Outbound E3 frames. However, the XRT72L56 Fram-
er IC lacks the current drive capability to be able to di-
rectly transmit this E3 data stream through some
transformer-coupled coax cable with enough signal
strength for it to be received by the remote receiver.
Therefore, in order to get around this problem, the
Framer IC requires the use of an LIU (Line Interface
Unit) IC. An LIU is a device that has sufficient drive
capability, along with the necessary pulse-shaping
circuitry to be able to transmit a signal through the
transmission medium in a manner that it can be reli-
ably received by the far-end receiver. Figure 178 pre-
sents a circuit drawing depicting the Framer IC inter-
facing to an LIU (XRT7300 DS3/E3/STS-1 Transmit
LIU).
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