XRT72L56 Datasheet, PDF (475/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
load Type value, then the XRT72L56 Framer IC will
generate this interrupt.
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
RO
RO
RO
0
0
0
BIT 4
RxFERF
Algo
RO
0
BIT 3
RxTMark
Algo
RO
0
BIT 2
BIT 1
RxPLDExp[2:0]
BIT 0
R/W
R/W
R/W
0
0
0
Enabling and Disabling the Detection of Payload
Type Mismatch Interrupt.
The user can enable or disable the Detection of Pay-
load Type Mismatch Interrupt by writing the appropri-
ate data into Bit 0 (RxPld Mis Interrupt Enable), within
the Rx E3 Interrupt Enable Register - 2, as indicated
below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
X
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
X
Setting this bit-field to “1 enables the Detection of
Payload Type Mismatch Interrupt. Conversely, setting
this bit-field to “0” disables the Detection of Payload
Type Mismatch Interrupt.
Servicing the Detection of Payload Type Mis-
match Interrupt
Whenever the XRT72L56 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT)
by driving it “Low”.
• It will set Bit 0 (RxPld Mis Interrupt Status), within
the Rx E3 Interrupt Enable Register -2 to “1”, as
indicated below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
1
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error Interrupt
Status
RUR
0
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
6.3.6.2.12 The Receive LAPD Message Interrupt
If the Receive LAPD Message Interrupt is enabled,
then the XRT72L56 Framer IC will generate an inter-
rupt anytime the Receive HDLC Controller block has
received a new LAPD Message frame from the Re-
mote Terminal Equipment, and has stored the con-
tents of this message into the Receive LAPD Mes-
sage buffer.
Enabling/Disabling the Receive LAPD Message
Interrupt
The user can enable or disable the Receive LAPD
Message Interrupt by writing the appropriate data into
Bit 1 (RxLAPD Interrupt Enable) within the Rx E3
LAPD Control Register, as indicated below.
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