XRT72L56 Datasheet, PDF (145/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
LCV - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
LCV - One-Second Count - High Byte
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
BIT 1
RO
0
BIT 0
RO
0
This Read-Only register, along with the LCV - One-
Second Accumulator Register - LSB (Address =
0x6F) contains a 16-bit representation of the number
of LCV (Line Code Violation) Events that have been
detected by the Receive DS3/E3 Framer block, within
the last one-second sampling period. This register
contains the MSB (or Upper-Byte) value of this 16 bit
expression.
2.4.8.14 One-Second Line Code Violation Accu-
mulator Register - LSB
LCV - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X6F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
LCV - One-Second Count - Low Byte
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
BIT 1
RO
0
BIT 0
RO
0
This Read-Only register, along with the LCV - One-
Second Accumulator Register - MSB (Address =
0x6E) contains a 16-bit representation of the number
of LCV (Line Code Violation) Events that have been
detected by the Receive DS3/E3 Framer block, within
the last One-Second sampling period. This register
contains the LSB (or Lower-Byte) value of this 16 bit
expression.
2.4.8.15 One-Second Frame Parity Error Accu-
mulator Register - MSB
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Frame Parity Error Count - High Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register, along with the Frame Parity
Errors - One-Second Accumulator Register - LSB
(Address = 0x71) contains a 16-bit representation of
the number of Frame Parity Errors that have been de-
tected by the Receive DS3/E3 Framer block, within
the last One-Second sampling period. This register
contains the MSB (or Upper-Byte) value of this 16 bit
expression.
NOTES:
1. For DS3 applications, the “Frame-Parity” Errors -
One Second Accumulator” register contains the
number of “P-bit” errors that have been detected in
the last one-second sampling period.
2. For E3, ITU-T G.751 applications, the “Frame-Par-
ity” Error - One Second Accumulator” register con-
tains the number of BIP-4 errors that have been
detected in the last one-second sampling period.
3. For E3, ITU-T G.832 applications, the “Frame-Par-
ity Error - One Second Accumulator” register con-
tains the number of BIP-8 errors that have been
detected in the last one-second sampling period.
2.4.8.16 One-Second Frame Parity Error Accu-
mulator Register - LSB
126