XRT72L56 Datasheet, PDF (168/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
DS3 terminals. Therefore, each DS3 M-frame con-
sists of a total of 28 F-bits. These F-bits exhibit a re-
peating pattern of "1001" within each F-frame. This
fact is also presented in Figure 40 and Figure 41,
which contains bit-fields that are designated as: F1,
F0, F0, and F1 (where F0 = "0", and F1 = "1").
Each of these bit-fields will be used by the Receive
DS3 Framer block, within the remote terminal equip-
ment, to perform Frame Acquisition and Frame Main-
tenance functions.
NOTE: For more information on how the Receive DS3
Framer uses these bit-fields, please see Section 3.3.2.
4.1.2 Performance Monitoring/Error Detection
Bits (Parity)
The DS3 Frame uses numerous bit fields to support
performance monitoring of the transmission link be-
tween the Local Transmitting Terminal and the Re-
mote Receiving Terminal. The DS3 frame can con-
tain two types of parity bits, depending upon the fram-
ing format chosen. P-bits are available in both the
M13 and C-bit Parity Formats. However, the C-bit
Parity format also includes additional CP-Parity bits.
P-Bits (Applies to M13 and C-Bit Parity Frame For-
mats)
Each DS3 M-frame consists of two (2) P-bits. These
two P-bits carry the parity information of the previous
DS3 frame for performance monitoring. These two P-
bits must be identical, within a given DS3 frame. The
Transmit Section will compute the even parity over all
4704 payload bits within a given DS3 frame, and in-
sert the resulting parity information in the P-bit fields
of the very next DS3 frame. The two P-bits are set to
"1" if the payload of the previous DS3 frame consists
of an odd number of "ones" in the frame. Conversely,
the two P-bits are set to zero if an even number of
"ones" is found in the payload of the previous DS3
frame. For information on how the Receive DS3
Framer handles P-bits, please see Section 3.3.2.6.1.
CP-(Path) Parity Bits (Applies to only the C-Bit
Parity Framing Format)
Each DS3 M-Frame consists of tw0 (2) CP-Bits.
These two bits have a very similar role to those of P-
Bits. Further, the XRT72L56 Framer IC processes
CP-Bits in an identical manner that it handles P-Bits.
However for some DS3 applications, there is a differ-
ence between P and CP-bits, that should be noted.
• P-Bits are used to support error detection of a DS3
data stream as it travels from one T.E. to the next.
(e.g., a single DS3 link between two T.E.)
• CP-Bits are used to support error detection of DS3
data stream as it travels from the Source T.E.
(where the DS3 Data Stream originated), to the
Sink T.E, (where the DS3 Data Stream is termi-
nated.)
NOTE: This transmission path from Source T.E. to Sink T.E.
may involve numerous T.E.
• P-Bits are verified and recomputed as it passes
through a Mid-Network T.E. (which is neither a
Source nor Sink T.E.)
• The values of the CP-Bits (as generated by the
Source T.E.) must be preserved as a DS3 frame
travels to the Sink T.E. (Through any number of
Mid-Network T.E.)
For more information on how CP-Bits are processed,
please see section 3.3.2.6.2
4.1.3 Alarm and Signaling-Related Overhead
Bits
The DS3 frame consists of mumerous bit-fields which
are used to support the handling of alarm and signal-
ing information. Each of these bit-fields are defined
below.
The Alarm Indication Signal (AIS) Pattern (C-Bit
Parity Framing Format only)
The Alarm Indication Signal (AIS) pattern is an alarm
signal that is inserted into the outbound DS3 stream
when a failure is detected by the Local Terminal. The
Transmit DS3 Framer will generate the AIS pattern as
defined in ANSI.T1.107a-1990, which is described as
follows.
VALID M-BITS, F-BITS, AND P-BITS
• All C-bits are zeros
• All X-bits are set to "1"
• A repeating "1010..." pattern is written into the pay-
load of the DS3 frames.
Consequently, no user (or payload) data will be trans-
mitted while the Transmit Section of the chip is trans-
mitting the AIS pattern.
The IDLE Condition Signal
The IDLE Condition signal is used to indicate that the
DS3 channel is functionally sound, but has not yet
been assigned any traffic. The Transmit Section will
transmit the IDLE Condition signal as defined in ANSI
T1.107a-1990, which is described as follows.
• Valid M-bits, F-bits, and P-bits
• The three CP-bits (F-frame #3) are zeros
• The X-bits are set to "1"
• A repeating "1100.." pattern is written into the pay-
load of the DS3 frames.
FEAC - Far End Alarm & Control (Only available
for the C-bit Parity Frame Format)
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