XRT72L56 Datasheet, PDF (63/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
FIGURE 19. MICROPROCESSOR INTERFACE TIMING - INTEL TYPE READ BURST ACCESS OPERATION
ALE_AS
A[11:0]
CS
D[7:0]
RD_DS
WR_R/W
RDY_DTCK
t76
Address of “Initial” Target Register (Offset = 0x00)
t68
Not Valid Valid Data at Offset =0x01
Not Valid Valid Data at Offset =0x02
t70
FIGURE 20. MICROPROCESSOR INTERFACE TIMING - INTEL TYPE WRITE BURST ACCESS OPERATION
ALE_AS
A(11:0)
Address of Initial Target Register (offset = 0x00)
CS
D(7:0)
RD_DS
WR_R/W
Not Valid
Valid Data at
Offset = 0x01
t₆₈
t₇₆
Not Valid
Valid Data at
Offset = 0x01
44