XRT72L56 Datasheet, PDF (484/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
TABLE 95: DESCRIPTION OF EACH OF THE RECEIVE HDLC CONTROLLER PINS
PIN NAME
RxIdle_n
Val_FCS_n
RxHDLCClk_n
RxHDLCDat_n[7:0]
TYPE
O
O
O
I
DESCRIPTION
Receive Idle (Flag Sequence) Indicator Signal
The combination of the RxIdle_n and Val_FCS_n output signals are used to convey
information about data that is being received via the Receive HDLC Controller block.
If RxIdle_n = High
The Receive HDLC Controller block will pulse this output pin "High" anytime the flag
sequence is present on the RxHDLCDat_n[7:0] output data bus.
If RxIdle_n and Val_FCS_n are both "High"
The Receive HDLC Controller block has received a complete HDLC frame, and has
determined that the FCS value (within this HDLC frame) is valid.
If RxIdle_n is "High" and Val_FCS_n is "Low"
The Receive HDLC Controller block has received a complete HDLC frame, and has
determined that the FCS value (within this HDLC frame) is invalid.
If RxIdle_n is "Low" and Val_FCS_n is "High"
The Receive HDLC Controller block has received an ABORT sequence.
Valid FCS Indicator Signal
Please see description above.
Receive HDLC Controller Clock Output signal:
The Receive HDLC Controller block outputs data (via the RxHDLCDat_n[7:0] output
pins) upon the rising edge of this clock signal. As a consequence, the user is advised
to configure/design his/her terminal equipment circuitry to sample the contents of the
RxHDLCDat_n[7:0] output pins, upon the falling edge of this clock signal.
Receive HDLC Controller - Output Data Bus:
The Receive HDLC Controller block outputs data (via these output pins) upon the ris-
ing edge of the RxHDLCClk_n clock signal. As a consequence, the user is advised to
configure/design his/her terminal equiment circuitry to sample the contents of this data
bus, upon the falling edge of this clock signal.
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