XRT72L56 Datasheet, PDF (222/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 36 relates the value of this bit-field to the Re-
ceive DS3 LIU Interface Input Mode.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 3
0
1
RECEIVE DS3 LIU INTERFACE INPUT MODE
.Bipolar Mode (Dual Rail): AMI or B3ZS Line Codes are Transmitted and Received.
Unipolar Mode (Single Rail) Mode of transmission and reception of DS3 data is selected.
NOTES:
1. The default condition is the Bipolar Mode.
2. This selection also effects the Transmit DS3 Framer
Line Interface Output Mode
4.3.1.2 Bipolar Decoding
If the Receive DS3 LIU Interface block is operating in
the Bipolar Mode, then it will receive the DS3 data
pulses via both the RxPOS, RxNEG, and the RxLi-
neClk input pins. Figure 75 presents a circuit dia-
gram illustrating how the Receive DS3 LIU Interface
block interfaces to the Line Interface Unit while the
Framer is operating in Bipolar mode. The Receive
DS3 LIU Interface block can be configured to decode
the incoming data from either the AMI or B3ZS line
codes.
FIGURE 75. ILLUSTRATION ON HOW THE RECEIVE DS3 FRAMER (WITHIN THE XRT72L56 FRAMER IC) BEING INTER-
FACED TO THEXRT73L03 LIU, WHILE THE FRAMER IS OPERATING IN BIPOLAR MODE (ONE CHANNEL SHOWN)
RxAVDD_0
DVDD_0
RxAIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[11:0]
READY_OUT*
ALE
RD*
WR*
XRT72L56_CS*
XRT72L56_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
U3
D9
A7
B8
A8
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
A9
B9
C9
T25
RxFrame_0
RxClk_0
RxSer_0
MOTO
RxPOS_0 ^H2
G1
RxNEG_0
K23
J26
K24
K25
L23
D7
D6
D5
D4
L24
L25
L26
D3
D2
D1
D0
R26
P25
P24
P23
A11
A10
A9
P26
N26
N25
N24
N23
M26
M25
A8
A7
A6
A5
A4
A3
A2
M24
A1
A0
J25
R24
Rdy_Dtck
U26
R23
T23
J24
ALE_AS
RD_DS
WR_RW
CS
INT
T24 _RESET
J4
RxLineClk_0
RLOL_0
ExtLOS_0
B6
J3
LLOOP_0
C8
B7
REQB_0
TAOS_0
DMO_0
TxLEV_0
C7
D8
D6
RLOOP_0 ^D10
C6
ENCODIS_0 (TxOFF_0)
J1
TxPOS_0
TxNEG_0 ^K4
TxLineClk_0 ^J2
R25 _NIBBLEINTF
B12
H3
C15
TxFrame_0
TxInClk_0
TxSer_0
XRT72L56_Ch_0
C4
0.01uF
C5
0.01uF
R7
4.7k
70 _RxAVDD0
48 _RxDVDD0
67
42
LOSTHR_0
HOST/HW
51 _RPOS0
50
RNEG0
49
RCLK0
U2
TxAVDD0 ²⁸
TxAVDD0 ³⁷
RTIP0 ⁷²
71
RRING0
C2
0.01uF
C3
0.01uF
TxAVDD_0
6 _T2 1
4
3
T3001
J1
BNC
1
XRT71D03_CS* (Optional)
57
55
RLOL_0
RLOS_0
61
62
CS
63
64
96
SCLK
SDI
SDO
REG_RESET*
117
TxOFF_0
33
TPDATA_0
32 _{TNDATA_0}
34
47
TCLK_0
EXCLK_0
29
TTIP0
TRING0 ²⁷
MTIP0 ³⁰
54 _RxDGND0
73 _RxAGND0
MRING0 ³¹
TxAGND0 ³⁹
TxAGND0 ²⁶
XRT73L03IV_Ch_0
R1
R2
37.4
37.4
C1
0.01uF
R3
31.6
R4
R5
31.6
270
R6
270
1 _T1 6
3
4
T3001
J2
BNC
1
203