XRT72L56 Datasheet, PDF (25/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
PIN DESCRIPTION FOR THE XRT72L56
PIN #
A18
A19
A20
A21
A22
A23
A24
PIN NAME
RxNib0[5]/
RxHDLCDat0[5]
RxNib3[5]/
RxHDLCDat3[5]
TxNibFrame[5]/
ValFCS[5]
TxOHInd[5]/
TxHDLCDat6[5]
TxAISEn[5]
TxNib0[5]/
TxHDLCDat0[5]
TxSer[5]/
SndMsg[5]
TYPE
O
O
O
DESCRIPTION
Receive Nibble Output - Channel 5, bit 0
The Framer outputs "Received data (from the Remote Terminal) to the local
Terminal Equipment via this pin along with bits 1,2 and 3.
The data at this pin is updated on the rising edge of the RxClk output signal.
NOTE: This output pin is active only if the Nibble-Parallel Mode has been
selected.
Receive HDLC Data Output - Cahnnel 5, bit 0:
This pin contains bit 0 RxHDLC data when the HDLC controller is turned on.
Receive Nibble Output - Channel 5, bit 3
See Description for pin A18
Receive HDLC Data Output - Channel 5, bit 3:
This pin contains bit 4 RxHDLC data when the HDLC controller is turned on.
See Description for Pin A12
O Transmit Overhead Data Indicator:
Indicates the overhead positions. When “high”, data placed by the data
source on TxSer line is ignored by the T3/E3 Framer. When TxPLClkEnb
register bit is “high”, it gives out a gapped clock with OH bit positions
blocked.
NOTE: For DS3 applications, this output pin is only active if the framer is
operating in the "Serial" Mode. This output pin will be pulled "low" if the
device is operating in the "Nibble-Parallel" Mode.
Transmit HDLC Data Output - 6:
I
This pin accepts bit 6 TxHDLC data when the HDLC controller is turned on.
I
Transmit AIS Input:
Setting this input pin "high" configures the Transmit Section to generate and
transmit an AIS Pattern.
Setting this input pin "low" configures the Transmit Section to generate E3
or DS3 traffic in a normal manner.
I
Transmit Nibble-Parallel Payload Data Input -Channel 5, bit 0:
The data applied to this pin ( alongwith bits 1,2 and 3) inserted into an out-
bound E3 or DS3 frame. The data is sampled at these input pins on the ris-
ing edge of TxNibClk signal.
NOTE: This input pin is active only if the Nibble-Parallel Mode has been
selected.
Transmit HDLC Data Input - Channel 5, bit 0:
This pin accepts bit 0 TxHDLC data when the HDLC controller is turned on.
I
Transmit Serial Payload Data :
Bit serial data is input.
If the framer is configured in “local time” mode, the data on this pin will be
sampled on the rising edge of TxlnClk. If the framer is configured in “Loop-
time “ mode, the data on this pin is sampled on the rising edge of RxOutClk.
NOTE: This input pin is active only if the Serial Mode has been selected.
Send Message:
This input pin must remain “High” during the entire length of the HDLC
packet, (including the FCS bytes) to be transmitted, when the HDLC control-
ler is turned on.
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