XRT72L56 Datasheet, PDF (316/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 124. ILLUSTRATION OF TWO EXAMPLES OF HDB3 ENCODING
Data 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
TxPOS
TxNEG
TxLineClk
Line Signal
0 00V
B00V
The user chooses between AMI or HDB3 line coding
by writing to bit 4 of the I/O Control Register (Address
= 0x01), as shown below.
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable TxLOC LOC
Disable AMI/ZeroSup* Unipolar/
RxLOC
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
Table 58 relates the content of this bit-field to the Bi-
polar Line Code that E3 Data will be transmitted and
received at.
TABLE 58: THE RELATIONSHIP BETWEEN BIT 4 (AMI/
HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT
E3 LIU INTERFACE BLOCK
BIT 4
0
1
BIPOLAR LINE CODE
HDB3
AMI
NOTES:
1. This bit is ignored if the Unipolar mode is selected.
2. This selection also effects the operation of the
Receive E3 LIU Interface block
5.2.5.2 TxLineClk Clock Edge Selection
The Framer also allows the user to specify whether
the E3 output data (via TxPOS and/or TxNEG output
pins) is to be updated on the rising or falling edges of
the TxLineClk signal. This selection is made by writ-
ing to bit 2 of the I/O Control Register, as depicted be-
low.
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable TxLOC LOC
Disable AMI/ZeroSup* Unipolar/
RxLOC
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
Table 59 relates the contents of this bit field to the
clock edge of TxClk that E3 Data is output on the Tx-
POS and/or TxNEG output pins.
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