XRT72L56 Datasheet, PDF (240/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
The LAPD receiver's actions are facilitated via the fol-
lowing two registers.
• Rx DS3 LAPD Control Register
• Rx DS3 LAPD Status Register
Operation of the LAPD Receiver
The LAPD Receiver, once enabled, will begin search-
ing for the boundaries of the incoming LAPD mes-
sage. The LAPD Message Frame boundaries are de-
lineated via the Flag Sequence octets (0x7E), as de-
picted in Figure 85.
FIGURE 85. LAPD MESSAGE FRAME FORMAT
Flag Sequence (8 bits)
SAPI (6-bits)
TEI (7 bits)
Control (8-bits)
C/R EA
EA
76 or 82 Bytes of Information (Payload)
FCS - MSB
FCS - LSB
Flag Sequence (8-bits)
Where: Flag Sequence = 0x7E
SAPI + CR + EA = 0x3C or 0x3E
TEI + EA = 0x01
Control = 0x03
The 16 bit FCS is calculated using CRC-16, x16 +
x12 + x5 + 1
mation field and the corresponding message type/
size follow:
CL Path Identification = 0x38 (76 bytes)
IDLE Signal Identification = 0x34 (76 bytes)
Test Signal Identification = 0x32 (76 bytes)
ITU-T Path Identification = 0x3F (82 bytes)
The microprocessor/microcontroller (at the remote
terminal), while assembling the LAPD Message
frame, will insert an additional byte at the beginning of
the information (payload) field. This first byte of the
information field indicates the type and size of the
message being transferred. The value of this infor-
The LAPD Receiver must be enabled before it can
begin receiving any LAPD messages. The LAPD Re-
ceiver can be enabled by writing a "1" into Bit 2 (Rx-
LAPD Enable) within the Rx DS3 LAPD Control Reg-
ister. The bit format of this register is depicted below.
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
BIT 4
Not Used
RO
RO
RO
RO
0
0
0
0
Once the LAPD Receiver has been enabled, it will be-
gin searching for the Flag Sequence octets (0x7E), in
the DL bit-fields, within the incoming DS3 frames.
BIT 3
BIT2
BIT 1
BIT 0
Not Used
RO
0
RxLAPD
Enable
R/W
1
RxLAPD
Interrupt
Enable
R/W
X
RxLAPD
Interrupt
Status
RUR
X
When the LAPD Receiver finds the flag sequence
byte, it will assert the Flag Present bit (Bit 0) within
the Rx DS3 LAPD Status Register, as depicted below.
RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19)
BIT 7
Not Used
BIT 6
RxAbort
BIT 5
BIT 4
RxLAPD Type[1, 0]
BIT 3
BIT2
RxCR Type RxFCS Error
X
X
X
X
The receipt of the Flag Sequence octet can mean
X
X
one of two things.
BIT 1
End of
Message
X
BIT 0
Flag
Present
1
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