XRT72L56 Datasheet, PDF (326/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
FIGURE 133. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND
RXNEG ARE TO BE SAMPLED ON THE RISING EDGE OF RXLINECLK
t42
RxLineClk
t38
t39
RxPOS
RxNEG
FIGURE 134. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND
RXNEG ARE TO BE SAMPLED ON THE FALLING EDGE OF RXLINECLK
RxLineClk
t40
t41
RxPOS
RxNEG
5.3.2 The Receive E3 Framer Block
The Receive E3 Framer block accepts decoded E3
data from the Receive E3 LIU Interface block, and
routes data to the following destinations.
• The Receive Payload Data Output Interface Block
• The Receive Overhead Data Output Interface
Block.
• The Receive E3 HDLC Controller Block
Figure 135 presents a simple illustration of the Re-
ceive E3 Framer block along with the associated
paths to the other functional blocks within the Framer
chip.
307