XRT72L56 Datasheet, PDF (3/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
FEATURES ................................................................................................................................................. 1
APPLICATIONS ........................................................................................................................................... 1
Figure 1. Block Diagram of the XRT72L56 ........................................................................................... 1
Figure 2. Pin Out of the XRT72L56 & 58 ............................................................................................... 2
ORDERING INFORMATION ............................................................................................ 2
PIN DESCRIPTION .......................................................................................................... 3
ELECTRICAL CHARACTERISTICS .............................................................................. 29
ABSOLUTE MAXIMUMS ............................................................................................................................. 29
DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 29
AC ELECTRICAL CHARACTERISTICS ......................................................................................................... 29
AC ELECTRICAL CHARACTERISTICS (CONT.) ............................................................................................ 31
1.0 Timing Diagrams ................................................................................................................................. 36
Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L56 Device is operating in
both the DS3 and Loop-Timing Modes ................................................................................................. 36
Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L56 Device is operating
in both the DS3 and Local-Timing Modes ............................................................................................. 36
Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L56 Device is
operating in both the DS3/Nibble and Looped-Timing Modes .............................................................. 37
Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L56 Device is
operating in the DS3/Nibble and Local-Timing Modes .......................................................................... 37
Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 38
Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 38
Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
rising edge of "TxLineClk" ..................................................................................................................... 39
Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
falling edge of "TxLineClk" .................................................................................................................... 39
Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
rising edge of "RxLineClk" ..................................................................................................................... 40
Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
falling edge of "RxLineClk" .................................................................................................................... 40
Figure 13. Receive Payload Data Output Interface Timing .................................................................. 41
Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ......................... 41
Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ................ 42
Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 42
Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations .............. 43
Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations .............. 43
Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ..................... 44
Figure 20. Microprocessor Interface Timing - Intel Type Write Burst Access Operation ..................... 44
Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 45
Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 45
Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........................................................ 46
2.0 The Microprocessor Interface Block ................................................................................................. 47
2.1 CHANNEL SELECTION WITHIN THE XRT72L56 DEVICE .......................................................................................... 47
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS A9, A10 AND A11 THE SELECTED CONFIGURATION REG-
ISTER BANK ............................................................................................................................................ 47
Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 48
2.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .............................................................................................. 48
TABLE 2: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH
THE INTEL AND MOTOROLA MODES .......................................................................................................... 49
TABLE 3: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTER-
FACE IS OPERATING IN THE INTEL MODE .................................................................................................. 49
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