XRT72L56 Datasheet, PDF (11/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................ 221
RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .......................................................................... 221
TABLE 41: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND
SIZE ...................................................................................................................................................... 222
Figure 86. Flow Chart depicting the Functionality of the LAPD Receiver .......................................... 223
4.3.4 The Receive Overhead Data Output Interface ...................................................................................... 223
Figure 87. A Simple Illustration of the Receive Overhead Output Interface block ............................. 224
TABLE 42: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ................................................................................................................................ 225
Figure 88. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 1). ............................................................................................................ 225
TABLE 43: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-
HFRAME WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT
PIN ....................................................................................................................................................... 226
Figure 89. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method
1). ........................................................................................................................................................ 228
TABLE 44: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2) ............................................................................................................. 229
Figure 90. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 2). ............................................................................................................ 230
TABLE 45: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME
WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN
231
Figure 91. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 233
4.3.5 The Receive Payload Data Output Interface ......................................................................................... 233
Figure 92. A Simple illustration of the Receive Payload Data Output Interface block ........................ 234
TABLE 46: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK .................................................................................................................................... 235
Figure 93. Illustration of the XRT72L56 DS3/E3 Framer IC being interfaced to the Receive Terminal Equip-
ment (Serial Mode Operation) ............................................................................................................. 236
Figure 94. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface
block of the XRT72L56 and the Terminal Equipment (Serial Mode Operation) .................................. 237
Figure 95. Illustration of the XRT72L56 DS3/E3 Framer IC being interfaced to the Receive Section of the
Terminal Equipment (Nibble-Mode Operation) ................................................................................... 238
Figure 96. An Illustration of the Behavior of the signals between the Receive Payload Data Output Interface
Block of the XRT72L56 and the Terminal Equipment (Nibble-Mode Operation). ............................... 239
4.3.6 Receive Section Interrupt Processing ................................................................................................... 239
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 240
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 240
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 241
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 241
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 242
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 242
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 242
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 243
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 243
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 244
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 244
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 245
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 245
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 245
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 246
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 246
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 246
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