XRT72L56 Datasheet, PDF (447/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
Finally, after the LAPD Receiver has received and
processed the newly received LAPD Message frame
(per steps 1 through 4, as described above), it will in-
form the local Microprocessor that a LAPD Message
frame has been received and is ready for user-sys-
tem handling. The LAPD Receiver will inform the Mi-
croprocessor/Microcontroller and the external circuit-
ry by:
• Generating a LAPD Message Frame Received
interrupt to the Microprocessor. The purpose of
this interrupt is to let the Microprocessor know that
the Receive LAPD Message buffer contains a new
PMDL Message that needs to be read and pro-
cessed. When the LAPD Receiver generates this
interrupt, it will set bit 0 (RxLAPD Interrupt Status)
within the Rx E3 LAPD Control Register to “1” as
depicted below.
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
DL from NR
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
RO
RO
RO
R/W
R/W
R/W
RUR
0
0
0
0
0
0
0
1
• Setting Bit 1 (End of Message) within the Rx E3
LAPD Status Register, to “1” as depicted below.
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19)
BIT 7
Not Used
BIT 6
Rx ABORT
BIT 5
BIT 4
RxLAPDType[1:0]
RO
RO
RO
RO
0
0
0
0
BIT 3
RxCR
Type
RO
0
BIT 2
RxFCS
Error
RO
0
BIT 1
End of
Message
RO
1
BIT 0
Flag
Present
RO
0
In summary, Figure 201 presents a flow chart depict-
ing how the LAPD Receiver functions.
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