XRT72L56 Datasheet, PDF (105/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
Bit 6 - SSM Message Interrupt Status
This Reset-upon-Read bit-field indicates whether or
not a Change of Synchronization Status Message
(SSM) Interrupt has occurred since the last read of
this register. This interrupt will occur whenever a
change in the contents of the SSM (within the in-
bound E3 data stream) has been detected.
If this bit-field has been set to “1”, then the Change of
SSM Interrupt has occurred since the last read of this
register. Conversely, if this bit-field has been set to
“0”, then the Change of SSM Interrupt has not oc-
curred since the last read of this register.
NOTE: This bit-field is invalid if the channel has been con-
figured to support the November 1995 revision of the ITU-T
G.832 Framing format for E3.
Bit 5 - SSM Out of Sequence Interrupt Status
This Reset-upon-Read bit-field indicates whether or
not the Change in SSM Out of Sequence State inter-
rupt has occurred since the last read of this register.
This interrupt will occur in response to either of the
following conditions.
1. The Receive Section losses sequence synchroni-
zation with the SSM data.
2. The Receive Section re-acquires sequence syn-
chronization with the SSM data.
NOTE: This bit-field is invalid if the Channel has been con-
figured to support the November 1995 revision of the ITU-T
G.832 Framing format for E3.
Bit 4 - COFA (Change of Frame Alignment) Inter-
rupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Change of Frame Alignment interrupt has occurred
since the last read of this register.
The Receive DS3/E3 Framer block will generate the
Change of Frame Alignment interrupt if it has detect-
ed a change in frame alignment in the incoming E3
frames.
Bit 3 - OOF (Receive E3 Framer) Interrupt Status
This Reset Upon Read bit-field is set to "1" if the Re-
ceive DS3/E3 Framer block has detected a Change in
the Out-of-Frame (OOF) Condition, since the last time
this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has
detected the appropriate conditions to declare an
OOF Condition.
2. When the Receive DS3/E3 Framer block has
transitioned from the OOF Condition (Frame
Acquisition Mode) into the In-Frame Condition
(Frame Maintenance mode).
NOTE: For more information of the OOF Condition, please
see Section 5.3.2.1.
Bit 2 - LOF (Loss of Frame) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if a
Change in LOF Condition interrupt has occurred
since the last read of this register.
The Receive DS3/E3 Framer block will generate the
Change in LOF Condition interrupt is response to ei-
ther of the following two occurrences.
1. Whenever the Receive DS3/E3 Framer block
transitions from the OOF Condition state into the
LOF Condition state, within the E3 Framing
Acquisition/Maintenance algorithm (per
Figure 194).
2. Whenever the Receive DS3/E3 Framer block
transitions from the FA1, FA2 Octet Verification
state to the In-frame state, within the E3 Framing
Acquisition/Maintenance algorithm (per
Figure 194).
Bit 1 - LOS (Loss of Signal) Interrupt Status
This Reset Upon Read bit will be set to "1", if the Re-
ceive DS3/E3 Framer block has detected a
Change in the LOS Status condition, since the last
time this register was read. This bit-field will be as-
serted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block detects
the occurrence of an LOS Condition (e.g., the
occurrence of 32 consecutive spaces in the
incoming E3 data stream), and
2. When the Receive DS3/E3 Framer block detects
the end of an LOS Condition (e.g., when the
Receive DS3/E3 Framer block detects a string 32
bits that does not contain a string of four consec-
utive "0’s").
The local µP can determine the current state of the
LOS condition by reading bit 6 of the Rx E3 Configu-
ration and Status Register (Address = 0x11).
NOTE: For more information in the LOS of Signal (LOS)
Alarm, please see Section 5.3.2.6.
Bit 0 - AIS Interrupt Status
This Reset Upon Read bit field will be set to "1", if the
Receive DS3/E3 Framer block has detected a
Change in the AIS condition, since the last time this
register was read. This bit-field will be asserted un-
der either of the following two conditions:
1. When the Receive DS3/E3 Framer block first
detects an AIS Condition in the incoming E3 data
stream.
2. When the Receive DS3/E3 Framer block has
detected the end of an AIS Condition in the
incoming E3 data stream.
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