XRT72L56 Datasheet, PDF (117/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
the Out-of-Frame (OOF) Condition, since the last time
this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has
detected the appropriate conditions to declare an
OOF Condition.
2. When the Receive DS3/E3 Framer block has
transitioned from the OOF Condition (Frame
Acquisition Mode) into the In-Frame Condition
(Frame Maintenance mode).
NOTE: For more information of the OOF Condition, please
see Section 4.3.2.2.
Bit 2 - LOF (Change in LOF Condition) Interrupt
Status
This Reset-upon-Read bit-field will be set to "1" if a
Change in LOF Condition interrupt has occurred
since the last read of this register.
The Receive DS3/E3 Framer block will generate the
Change in LOF Condition interrupt is response to ei-
ther of the following two occurrences.
1. Whenever the Receive DS3/E3 Framer block
transitions from the OOF Condition state into the
LOF Condition state, within the E3 Framing
Acquisition/Maintenance algorithm (per Figure
114).
2. Whenever the Receive DS3/E3 Framer block
transitions from the FA1, FA2 Octet Verification
state to the In-frame state, within the E3 Framing
Acquisition/Maintenance algorithm (per Figure
114).
Bit 1 - LOS (Change in LOS Condition) Interrupt
Status
This Reset Upon Read bit will be set to "1", if the Re-
ceive DS3/E3 Framer block has detected a Change in
the LOS Status condition, since the last time this reg-
ister was read. This bit-field will be asserted under ei-
ther of the following two conditions:
1. When the Receive DS3/E3 Framer block detects
the occurrence of an LOS Condition (e.g., the
occurrence of 32 consecutive spaces in the
incoming E3 data stream), and
2. When the Receive DS3/E3 Framer block detects
the end of an LOS Condition (e.g., when the
Receive DS3/E3 Framer block detects a string 32
bits that does not contain a string of four consec-
utive "0’s").
The local µP can determine the current state of the
LOS condition by reading bit 6 of the Rx E3 Configu-
ration and Status Register (Address = 0x11).
NOTE: For more information in the LOS of Signal (LOS)
Alarm, please see Section 4.3.2.7.
Bit 0 - AIS (Change in AIS Condition) Interrupt
Status
This Reset Upon Read bit field will be set to "1", if the
Receive DS3/E3 Framer block has detected a
Change in the AIS condition, since the last time this
register was read. This bit-field will be asserted un-
der either of the following two conditions:
1. When the Receive DS3/E3 Framer block first
detects an AIS Condition in the incoming E3 data
stream.
2. When the Receive DS3/E3 Framer block has
detected the end of an AIS Condition in the
incoming E3 data stream.
The local µP can determine the current state of the
AIS condition by reading bit 7 of the Rx E3 Configura-
tion and Status Register (Address = 0x11).
NOTE: For more information on the AIS Condition please
see Section 4.3.2.8.
2.4.4.6 Receive E3 Interrupt Status Register -
2 (E3, ITU-T G.751)
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
FERF
Interrupt
Status
RO
RO
RO
RO
RUR
0
0
0
0
0
BIT 2
BIP-4
Error
Interrupt
Status
RUR
0
BIT 1
Framing
Error
Interrupt
Status
RUR
0
BIT 0
Not Used
RUR
0
Bit 3 - FERF (Change in FERF Condition) Interrupt
Status
This Reset Upon Read bit will be set to '1' if the Re-
ceive DS3/E3 Framer block has detected a Change in
the Rx FERF Condition, since the last time this regis-
ter was read.
This bit-field will be asserted under either of the fol-
lowing two conditions.
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