XRT72L56 Datasheet, PDF (184/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 52. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L56 FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-SLAVE) OPER-
ATION
44.736MHz Clock Source
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
11.184MHz
4
VCC
TxInClk
TxNibClk
TxNib[3:0]
TxFrameRef
NibInt
Terminal Equipment
XRT72L5x DS3 Framer
Mode 5 Operation of the Terminal Equipment
In Figure 52 both the Terminal Equipment and the
XRT72L56 will be driven by an external 11.184MHz
clock signal. The Terminal Equipment will receive the
11.184MHz clock signal via the DS3_Nib_Clock_In
input pin. The XRT72L56 will output the 11.184MHz
clock signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data
on the DS3_Data_Out[3:0] pins, upon the rising edge
of the signal at the DS3_Clock_In input pin.
NOTE: The DS3_Data_Out[3:0] output pins of the Terminal
Equipment is electrically connected to the TxNib[3:0] input
pins.
The XRT72L56 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
In this case, the Terminal Equipment has the respon-
sibility of providing the framing reference signal by
pulsing the Tx_Start_of_Frame output pin (and in
turn, the TxFrameRef input pin of the XRT72L56)
"High" for one bit-period, coincident with the first nib-
ble of a new DS3 frame. Once the XRT72L56 detects
the rising edge of the input at its TxFrameRef input
pin, it will begin generation of a new DS3 frame.
Finally, the XRT72L56 will always internally generate
the Overhead bits, when it is operating in both the
DS3 and Nibble-parallel modes. The XRT72L56 will
pull the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L56
and the Terminal Equipment for DS3 Mode 5 Opera-
tion is illustrated in Figure 53.
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