XRT72L56 Datasheet, PDF (386/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 165. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L56 FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIME/FRAME-SLAVE) OPERA-
TION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz Clock Source
8.592MHz
4
TxInClk
TxNibClk
NibInt
TxNib[3:0]
TxFrameRef
TxOH_Ind
VCC
Terminal Equipment
XRT72L5x E3 Framer
Mode 5 Operation of the Terminal Equipment
In Figure 165 both the Terminal Equipment and the
XRT72L56 will be driven by an external 8.592MHz
clock signal. The Terminal Equipment will receive the
8.592MHz clock signal via the E3_Nib_Clock_In input
pin. The XRT72L56 will output the 8.592MHz clock
signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data
on the E3_Data_Out[3:0] pins, upon the rising edge
of the signal at the E3_Clock_In input pin.
NOTE: The E3_Data_Out[3:0] output pins of the Terminal
Equipment is electrically connected to the TxNib[3:0] input
pins.
The XRT72L56 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
In this case, the Terminal Equipment has the respon-
sibility of providing the framing reference signal by
pulsing the Tx_Start_of_Frame output pin (and in
turn, the TxFrameRef input pin of the XRT72L56)
"High" for one bit-period, coincident with the first bit of
a new E3 frame. Once the XRT72L56 detects the ris-
ing edge of the input at its TxFrameRef input pin, it
will begin generation of a new E3 frame.
Finally, the XRT72L56 will always internally generate
the Overhead bits, when it is operating in both the E3
and Nibble-parallel modes. The XRT72L56 will pull
the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L56
and the Terminal Equipment for E3 Mode 5 Operation
is illustrated in Figure 166.
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