XRT72L56 Datasheet, PDF (73/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
the µC/µP. The XRT72L56 DS3/E3 Framer will
indicate that this data can be read by asserting
the RDY_DTCK (DTACK) signal.
8. After the µC/µP detects the RDY_DTCK signal
(from the XRT72L56 DS3/E3 Framer) it will termi-
nate the Read Cycle by toggling the RD_DS
(Data Strobe) input pin "High".
Figure 27 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals
during a Motorola-type Programmed I/O Read Opera-
tion.
FIGURE 27. ILLUSTRATION OF THE BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS, DURING A MOTOROLA-
TYPE PROGRAMMED I/O READ OPERATION
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of target Register
Not Valid
Valid Data
2.3.2.1.2.2 The Motorola Mode Write Cycle
Whenever a Motorola-type µC/µP wishes to write a
byte or word of data into a register or buffer location,
within the Framer, it should do the following.
1. Assert the ALE_AS (Address Select) input pin by
toggling it "Low". This step enables the Address
Bus input drivers (within the Framer chip).
2. Place the address of the target register or buffer
location (within the Framer), on the Address Bus
input pins, A[11:0].
3. While the µC/µP is placing this address value
onto the Address Bus, the Address-Decoding cir-
cuitry (within the user's system) should assert the
CS (Chip Select) input pins of the Framer by tog-
gling it "Low". This step enables further commu-
nication between the µC/µP and the Framer
Microprocessor Interface block.
4. After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address
Setup time), the µC/µP should toggle the
ALE_AS input pin "High". This step causes the
Framer device to latch the contents of the
Address Bus into its own circuitry. At this point,
the Address of the register or buffer location
(within the Framer), has now been selected.
5. Further, the µC/µP should indicate that this cur-
rent bus cycle is a Write operation by toggling the
WR_R/W (R/W) input pin "Low".
6. The µC/µP should then place the byte or word
that it intends to write into the target register, on
the bi-directional data bus, D[7:0].
7. Next, the µC/µP should initiate the bus cycle by
toggling the RD_DS (Data Strobe) input pin
"Low". When the XRT72L56 DS3/E3 Framer
senses that the WR_R/W (R/W*) input pin is
"High" and that the RD_DS (Data Strobe) input
pin has toggled "Low", it will enable the input driv-
ers of the bi-directional data bus, D[7:0].
8. After waiting the appropriate time, for this newly
placed data to settle on the bi-directional data
bus (e.g., the Data Setup time) the Framer will
assert the RDY_DTCK output signal.
9. After the µC/µP detects the RDY_DTCK signal
(from the Framer), the µC/µP should toggle the
RD_DS input pin "High". This action accom-
plishes two things.
a. It latches the contents of the bi-directional data
bus into the XRT72L56 DS3/E3 Microprocessor
Interface block.
b. It terminates the Write cycle.
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