XRT72L56 Datasheet, PDF (121/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
Writing a '1' to this bit-field invokes this command,
causing the Transmit DS3/E3 Framer block to gener-
ate an all '0' pattern.
NOTE: For more information on this feature, please see
Section 3.2.4.2.1.5.
Bit 2 - FERF on LOS
This Read/Write bit-field allows the user to configure
the Transmit DS3/E3 Framer block to generate a Yel-
low Alarm if the Near-End Receive DS3/E3 Framer
block (within the same channel) detects a LOS (Loss
of Signal) Condition.
Writing a "1" to this bit-field enables this feature. Writ-
ing a "0" to this bit-field disables this feature.
NOTE: For more information on this feature, please see
Section 3.2.4.2.1.6.
Bit 1 - FERF on OOF
This Read/Write bit-field allows the user to configure
the Transmit DS3/E3 Framer block to generate a Yel-
low Alarm if the Near-End Receive DS3/E3 Framer
block (within the same channel) detects an OOF
(Out-of-Frame) Condition.
Writing a "1" to this bit-field enables this feature. Writ-
ing a "0" to this bit-field disables this feature.
NOTE: For more information on this feature, please see
Section 3.2.4.2.1.7.
Bit 0 - FERF on AIS
This Read/Write bit-field allows the user to configure
the Transmit DS3/E3 Framer block to generate a Yel-
low Alarm if the Near-End Receive DS3/E3 Framer
block (within the same channel) detects an AIS
(Alarm Indication Signal) Condition.
Writing a "1" to this bit-field enables this feature. Writ-
ing a "0" to this bit-field disables this feature.
NOTE: For more information on this feature, please see
Section 3.2.4.2.1.8.
2.4.5.2 Transmit DS3 FEAC Configuration &
Status Register (DS3 Applications)
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
Tx FEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
GO
TxFEAC
Busy
RO
RO
RO
R/W
RUR
R/W
R/W
RO
0
0
0
0
0
0
0
0
Bit 4 - Tx FEAC Interrupt Enable
This Read-Write bit-field permits the user to enable or
disable the Transmit FEAC Interrupt.
Setting this bit-field to “0” disables this interrupt.
Conversely, setting this bit-field to “1” enables this in-
terrupt.
Bit 3 - TxFEAC Interrupt Status
This Read-Only bit-field indicates whether or not the
FEAC Message Transmission Complete interrupt has
occurred since the last read of this register. This in-
terrupt will occur once the Transmit FEAC Processor
has finished its 10th transmission of the 16 bit FEAC
Message (6 bit FEAC Code word + 10 framing bits).
The purpose of this interrupt is to let the local µP
know that the Transmit FEAC Processor has complet-
ed its transmission of its latest FEAC Message and is
now ready to transmit another FEAC Message.
If this bit-field is "0", then the FEAC Message Trans-
mission Complete interrupt has NOT occurred since
the last read of this register.
If this bit-field is “1”, then the FEAC Message Trans-
mission Complete interrupt has occurred since the
last read of this register.
NOTE: For more information on the Transmit FEAC Proces-
sor, please see Section 3.2.3.1.
Bit 2 - TxFEAC Enable
This Read/Write bit-field allows the user to enable or
disable the Transmit FEAC Processor. The Transmit
FEAC Processor will NOT function until it has been
enabled.
Writing a "0" to this bit-field disables the Transmit
FEAC Processor. Writing a "1" to this bit-field en-
ables the Transmit FEAC Processor.
Bit 1 - TxFEAC Go
This bit-field allows the user to invoke the Transmit
FEAC Message command. Once this command has
been invoked, the Transmit FEAC Processor will do
the following:
• Encapsulate the 6 bit FEAC code word, from the Tx
DS3 FEAC Register (Address = 0x32) into a 16 bit
FEAC Message
102