XRT72L56 Datasheet, PDF (362/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
5.3.6.2.3 The Change in Receive LOF Condi-
tion Interrupt
If the Change in Receive LOF Condition Interrupt is
enabled, then the XRT72L56 Framer IC will generate
an interrupt in response to either of the following con-
ditions.
1. When the XRT72L56 Framer IC declares an LOF
(Out of Frame) Condition, and
2. When the XRT72L56 Framer IC clears the LOF
condition.
Conditions causing the XRT72L56 Framer IC to
declare an LOF Condition.
• If the Receive E3 Framer block (within the
XRT72L56 Framer IC) detects Framing Bit errors,
within four consecutive incoming E3 frames, and is
not capable of transition back into the In-Frame
state within a 1ms or 3ms period.
Conditions causing the XRT72L56 Framer IC to
clear the LOF Condition.
• If the Receive E3 Framer block transitions from the
OOF Condition state to the LOF Condition state
(see Figure 115).
• If the Receive E3 Framer block transitions back into
the In-Frame state.
Enabling and Disabling the Change in Receive
LOF Condition Interrupt
The user can enable or disable the Change in Re-
ceive LOF Condition Interrupt, by writing the appropri-
ate value into Bit 3 (LOF Interrupt Enable), within the
RxE3 Interrupt Enable Register - 1, as indicated be-
low.
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
X
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change in Receive LOF Condition
Interrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “Low”.
• It will set Bit 6 (LOF Interrupt Status), within the Rx
E3 Interrupt Status Register - 1 to “1”, as indicated
below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
0
0
1
1
1
5.3.6.2.4 The Change in Receive AIS Condition
Interrupt
If the Change in Receive AIS Condition Interrupt is
enabled, then the XRT72L56 Framer IC will generate
an interrupt in response to either of the following con-
ditions.
1. When the XRT72L56 Framer IC declares an AIS
(Loss of Signal) Condition, and
2. When the XRT72L56 Framer IC clears the AIS
condition.
Conditions causing the XRT72L56 Framer IC to
declare an AIS Condition.
• If the XRT72L56 Framer IC detects 7 or less “0”
within 2 consecutive E3 frames.
Conditions causing the XRT72L56 Framer IC to
clear the AIS Condition.
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