XRT72L56 Datasheet, PDF (53/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t_60A Rising edge of "RxOHFrame" to rising edge of
910
"RxOHEnable" delay
220
MAX.
930
UNITS
ns
CONDITIONS
DS3 Applications
240
ns ^{E3, ITU-T G.832}
Applications
t_60B “RxOH” Data Valid to rising edge of
"RxOHEnable" delay
25
32
ns ^{E3, ITU-T G.751}
Applications
910
930
ns ^{DS3 Applications}
420
440
ns ^{E3, ITU-T G.832}
Applications
25
Microprocessor Interface - Intel (See Figure 17)
t₆₄ A11 - A0 Setup Time to ALE_AS Low
4
t₆₅ A11 - A0 Hold Time from ALE_AS Low.
2
Intel Type Read Operations (See Figure 17 and Figure 19)
t₆₆ RD_DS, WR_R/W Pulse Width
60
t₆₇ Data Valid from RD_DS Low.
6
t₆₈ Data Bus Floating from RD_DS High
7
t₆₉ ALE to RD Time
4
t₇₀₁ RD Time to "NOT READY" (e.g., RDY_DTCK tog-
gling "Low")
t₇₀ RD to READY Time (e.g., RDY_DTCK toggling
15
"high")
t₇₆ Minimum Time between Read Burst Access (e.g.,
30
the rising edge of RD to falling edge of RD)
Intel Type Write Operations (Figure 18 and Figure 20)
t₇₁ Data Setup Time to WR_R/W High
4
t₇₂ Data Hold Time from WR_RW* High
2
t₇₃ High Time between Reads and/or Writes
30
t₇₄ ALE to WR Time
4
t₇₇ Min Time between Write Burst Access (e.g., the ris- 30
ing edge of WR to the falling edge of WR)
t₇₇₀ CS Assertion to falling edge of WR_R/W
20
Microprocessor Interface - Motorola Read Operations (See Figure 21)
t₇₈ A11 - A0 Setup Time to falling edge of ALE_AS
5
32
ns ^{E3, ITU-T G.751}
Applications
ns
ns
ns
11
ns
12
ns
ns
6
ns
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
34