XRT72L56 Datasheet, PDF (224/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 77. ILLUSTRATION OF TWO EXAMPLES OF B3ZS DECODING
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
00 V
Line Signal
RxPOS
RxNEG
B 0V
4.3.1.2.3 Line Code Violations
The Receive DS3 LIU Interface block will also check
the incoming DS3 data stream for line code viola-
tions. For example, when the Receive DS3 LIU Inter-
face block detects a valid bipolar violation (e.g., in
B3ZS line code), it will substitute three zeros into the
binary data stream. However, if the bipolar violation
is invalid, then an LCV (Line Code Violation) is
flagged and the PMON LCV Event Count Register
(Address = 0x50 and 0x51) will also be incremented.
Additionally, the LCV-One Second Accumulation Reg-
isters (Address = 0x6E and 0x6F) will be increment-
ed. For example: If the incoming DS3 data is B3ZS
encoded, the Receive DS3 LIU Interface block will al-
so increment the LCV One Second Accumulation
Register if three (or more) consecutive zeros are re-
ceived.
II/O CONTROL REGISTER (ADDRESS = 0X01)
4.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the
RxPOS and the RxNEG input pins are clocked into
the Receive DS3 LIU Interface block via the RxLi-
neClk signal. The Framer IC allows the user to spec-
ify which edge (e.g, rising or falling) of the RxLineClk
signal will sample and latch the signal at the RxPOS
and RxNEG input signals into the Framer IC. This
feature was included in the XRT72L56 design in order
to insure that the user can always meet the RxPOS
and RxNEG to RxLineClk set-up and hold time re-
quirements. The user can make this selection by
writing the appropriate data to bit 1 of the I/O Control
Register, as depicted below.
BIT 7
BIT 6
BIT 5
BIT 4
Disable
TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 37 depicts the relationship between the value of
this bit-field to the sampling clock edge of RxLineClk.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
TABLE 37: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER,
AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL
RXCLKINV
(BIT 1)
RESULT
0
Rising Edge:
RxPOS and RxNEG are sampled at the rising edge of RxLineClk. See Figure 78 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
1
Falling Edge:
RxPOS and RxNEG are sampled at the falling edge of RxLineClk. See Figure 79 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
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