XRT72L56 Datasheet, PDF (440/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
FIGURE 199. ILLUSTRATION OF THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME (TO THE
REMOTE TERMINAL) WITH THE FEBE BIT (WITHIN THE MA BYTE-FIELD) SET TO “1”
Local Terminal
FEBE bit
x1xxxxxx
Transmit E3
Framer
Receive E3
Framer
MA Byte
Remote
Terminal
In additional to the FEBE bit-field signaling, the Re-
ceive E3 Framer block will generate the BIP-8 Error
Interrupt to the Microprocessor. Hence, it will set bit 2
(BIP-8 Error Interrupt Status) to “1”, as depicted be-
low.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TTB
Change
Interrupt
Status
Not Used
FEBE
Interrupt
Status
FERF
Interrupt
Status
BIP-8
Error
Interrupt
Status
Framing
Byte Error
Interrupt
Status
RxPld
Mis
Interrupt
Status
RO
RUR
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Finally, the Receive E3 Framer block will increment
the PMON Parity Error Count registers. The byte for-
mat of these registers are presented below.
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
421