XRT72L56 Datasheet, PDF (341/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
FIGURE 142. LAPD MESSAGE FRAME FORMAT
Flag Sequence (8 bits)
SAPI (6-bits)
TEI (7 bits)
Control (8-bits)
C/R EA
EA
76 or 82 Bytes of Information (Payload)
FCS - MSB
FCS - LSB
Flag Sequence (8-bits)
Where: Flag Sequence = 0x7E
SAPI + CR + EA = 0x3C or 0x3E
TEI + EA = 0x01
Control = 0x03
The 16 bit FCS is calculated using CRC-16, x16 +
x12 + x5 + 1
The local µP (at the remote terminal), while assem-
bling the LAPD Message frame, will insert an addi-
tional byte at the beginning of the information (pay-
load) field. This first byte of the information field indi-
cates the type and size of the message being trans-
ferred. The value of this information field and the
corresponding message type/size follow:
CL Path Identification = 0x38 (76 bytes)
IDLE Signal Identification = 0x34 (76 bytes)
Test Signal Identification = 0x32 (76 bytes)
ITU-T Path Identification = 0x3F (82 bytes)
Enabling and Configuring the LAPD Receiver
Before the LAPD Receiver can begin to receive and
process incoming LAPD Message frames, the user
must do two things.
1. Enabling the LAPD Receiver
The LAPD Receiver must be enabled before it can
begin receiving and processing any LAPD Message
frames. The LAPD Receiver can be enabled by writ-
ing a “1” to Bit 2 (RxLAPD Enable) of the Rx E3 LAPD
Control Register, as indicated below.
)
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
RxLAPD
Interrupt Enable Interrupt Enable
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
0
0
Once the LAPD Receiver has been enabled, it will be-
gin searching for the Flag Sequence octet (0x7E), in
the “N” bit-fields within each incoming E3 frame.
When the LAPD Receiver finds the flag sequence
byte, it will assert the Flag Present bit (Bit 0) within
the Rx E3 LAPD Status Register, as depicted below.
322