XRT72L56 Datasheet, PDF (108/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
table relates the contents of these bit-fields to the
LAPD Message type/size.
RXLAPDTYPE[1:0]
LAPD MESSAGE FRAME TYPE
PMDL MESSAGE SIZE (INFORMATION
SECTION)
00
CL Path Identification Type
76 Bytes
01
Idle Signal Identification Type
76 Bytes
10
Test Signal Identification Type
76 Bytes
11
ITU-T Path Identification Type
82 Bytes
Bit 3 - Rx CR Type
This Read-Only bit-field indicates the state of the C/R
bit-field, within octet # 2 of the most recently received
LAPD Message frame.
Bit 2 - Rx FCS Error
This Read-Only bit-field indicates whether or not the
LAPD Receiver has detected an FCS (Frame Check
Sequence) error, in the most recently received LAPD
Message frame. This bit-field is set to "0" if the LAPD
Receiver does not detect an FCS error in this LAPD
Message frame. Conversely, this bit-field is set to "1"
if the LAPD Receiver does detect an FCS error in this
LAPD Message frame.
NOTE: For a more detailed discussion on the LAPD
Receiver's handling of the FCS bytes, please see Section
5.3.3.
Bit 1 - EndOfMessage
The LAPD Receiver will assert this read-only bit-field,
when it has received a complete LAPD Message
frame. This bit-field, along with the Receipt of New
LAPD Message frame interrupt, serves to inform the
local µP that the Receive LAPD Message buffer con-
tains a new PMDL message that needs to be read
and processed.
This bit-field is cleared (to "0") upon reading this reg-
ister.
Bit 0 - Flag Present
The LAPD Receiver will assert this read-only bit-field
when it is currently detecting the Flag Sequence octet
(7Eh) in the incoming LAPD channel (e.g., either the
GC or the NR byte-field, within each E3 frame). The
LAPD Receiver will negate this bit-field when it is no
longer receiving the Flag Sequence octet in the in-
coming LAPD channel.
2.4.3.9 Receive E3 NR Byte Register (E3, ITU-T
G.832)
RXE3 NR BYTE REGISTER (ADDRESS = 0X1A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxNR[7:0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register contains the value of the NR
byte, within the most recently received E3 frame.
Please see Section 5.3.3 for a more detailed discus-
sion on this register.
2.4.3.10 Receive E3 GC Byte Register (E3, ITU-
T G.832)
RXE3 GC BYTE REGISTER (ADDRESS = 0X1B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxGC[7:0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
89