XRT72L56 Datasheet, PDF (200/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
1. Write the 6-bit FEAC code (to be sent) into the Tx
DS3 FEAC Register.
2. Enable the Transmit FEAC Processor.
3. Initiate the Transmission of the FEAC Message.
Each of these steps will be described in detail below.
STEP 1 - Writing in the six bit FEAC Codeword (to
be sent)
In this step, the µP/µC writes the six bit FEAC code
word into the Tx DS3 FEAC Register. The bit format
of this register is presented below.
TX DS3 FEAC REGISTER (ADDRESS = 0X32)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
RO
0
TxFEAC[5]
R/W
d5
TxFEAC[4]
R/W
d4
TxFEAC[3]
R/W
d3
STEP 2 - Enabling the Transmit FEAC Processor
In order to enable the Transmit FEAC Processor
(within the Transmit DS3 HDLC Controller block) the
BIT 3
BIT2
BIT 1
BIT 0
TxFEAC[2]
R/W
d2
TxFEAC[1]
R/W
d1
TxFEAC[0]
R/W
d0
Not Used
R0
0
user must write a 1 into bit 2 (Tx FEAC Enable) within
the Tx DS3 FEAC Configuration and Status Register,
as depicted below.
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
Not Used
Not Used
RO
RO
RO
x
x
x
TxFEAC
Interrupt
Enable
R/W
x
At this point, the Transmit FEAC Processor can be
commanded to begin transmission (See STEP 3).
STEP 3 - Initiate the Transmission of the FEAC
Message
BIT 3
BIT2
BIT 1
BIT 0
TxFEAC
Interrupt
Status
RO
x
TxFEAC
Enable
R/W
1
TxFEAC
Go
R/W
X
TxFEAC
Busy
R0
X
The user can initiate the transmission of the FEAC
code word (residing in the Tx DS3 FEAC register) by
writing a 1 to bit 1 (Tx FEAC Go) within the Tx DS3
FEAC Configuration and Status register, as depicted
below.
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
Not Used
Not Used
RO
RO
RO
x
x
x
TxFEAC
Interrupt
Enable
R/W
x
NOTE: While executing this particular write operation, the
user should write the binary value 000xx110b into the Tx
DS3 FEAC Configuration and Status Register. By doing
this the user insures that a 1 is also being written to Bit 2
(Tx FEAC Enable) of the register, in order to keep the
Transmit FEAC Processor enabled.
Once this step has been completed, the Transmit
FEAC Processor will proceed to transmit the 16 bit
FEAC code via the outbound DS3 frames. This 16 bit
FEAC message will be transmitted repeatedly 10
consecutive times. Hence, this process will require a
total of 160 DS3 Frames. During this process the Tx
FEAC Busy bit (Bit 0, within the Transmit DS3 FEAC
Configuration and Status register) will be asserted,
BIT 3
BIT2
BIT 1
BIT 0
TxFEAC
Interrupt
Status
RO
x
TxFEAC
Enable
R/W
1
TxFEAC
Go
R/W
1
TxFEAC
Busy
R0
X
indicating that the Tx FEAC Processor is currently
transmitting the FEAC Message to the remote Termi-
nal. This bit-field will toggle to "0" upon completion of
the 10th transmission of the FEAC Code Message.
The Transmit FEAC Processor will generate an inter-
rupt (if enabled) to the local µP/µC, upon completion
of the 10th transmission of the FEAC Message. The
purpose of having the Framer IC generating this inter-
rupt is to let the local µP/µC know that the Transmit
FEAC Processor is now available and ready to trans-
mit a new FEAC message. Finally, once the Transmit
FEAC Processor has completed its 10th transmission
of a FEAC Code Message it will then begin sending
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