XRT72L56 Datasheet, PDF (328/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 136. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER E3 FRAME ACQUISITION/MAINTENANCE
ALGORITHM
FAS
Pattern
Search
FAS pattern is
detected once
FAS
Pattern
Verification
FAS Pattern is
not detected
LOF
Condition
FAS Pattern is
verified once
8 or 24 framing periods
of operating in the
OOF condition
(user-selectable)
OOF
Condition
3 consecutive
Valid Frames
4 consecutive
In-valid Frames
In Frame
Frame Maintenance
Mode
FIGURE 137. ILLUSTRATION OF THE E3, ITU-T G.751 FRAMING FORMAT
1
10 11 12
Frame
Alignment
Signal
AN
384 385
768 769
1152 1153
1532
1536
Data
Data
Data
Data
BIP-4
if Selected
Framing Alignment Signal Pattern = 1111010000
When the Receive E3 Framer block detects the FAS
pattern, it will then transition over to the FAS Pattern
Verification state, per Figure 137.
The FAS Pattern Verification State
Once the Receive E3 Framer block has detected an
“1111010000” pattern, it must verify that this pattern
is indeed the FAS pattern and not some other set of
bits, within the E3 frame, mimicking the FAS Pattern.
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