XRT72L56 Datasheet, PDF (262/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
2. It should transmit the appropriate FEAC Message
(per Bellcore GR-499-CORE), to the Remote Ter-
minal Equipment, indicating that the Service
Affecting condition has been cleared.
4.3.6.2.3 The Change of State of Receive AIS
Interrupt
If the Change of State on Receive AIS (Alarm Indica-
tion Signal) Interrupt is enabled, then the XRT72L56
Framer IC will generate an interrupt in response to ei-
ther of the following conditions.
1. When the XRT72L56 Framer IC detects an AIS
pattern, in the incoming DS3 data stream, and
2. When the XRT72L56 Framer IC no longer detects
the AIS pattern in the incoming DS3 data stream.
Conditions causing the XRT72L56 Framer IC to
declare an AIS condition
• If the Receive DS3 Framer block (within the
XRT72L56 Framer IC) detects at least 63 DS3
frames, which contains the AIS pattern.
Conditions causing the XRT72L56 Framer IC to
clear the AIS condition.
• Whenever, the Receive DS3 Framer block detects
63 DS3 frames, which do not contain the AIS pat-
tern.
Enabling and Disabling the Change of State on
Receive AIS Interrupt:
The user can enable or disable the Change of State
on Receive AIS Interrupt, by writing the appropriate
value into Bit 5 (AIS Interrupt Enable) within the
RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change of State on Receive AIS In-
terrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "Low".
• It will set Bit 5 (AIS Interrupt Status) within the
RxDS3 Interrupt Status Register, to “1”, as indi-
cated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
1
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters a
Change in AIS on Receive interrupt, it should do the
following.
1. It should determine the current state of the AIS
condition. Recall, that this interrupt can gener-
ated, whenever the XRT72L56 Framer declares
or clears the AIS defects. Hence, the user can
determine the current state of the AIS defect by
reading the state of Bit 7 (RxAIS), within the
RxDS3 Configuration & Status Registers, as illus-
trated below
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