82870P2P64H2 Datasheet, PDF (99/217 Pages) –

Register Description
R
3.4.1.9
SS—Subsystem Identifier Register (D28,30: F0)
Offset:
2C–2Fh
Default Value: 00000000h
Attribute:
Size:
R/WO
32 bits
This register is initialized to logic 0 by the assertion of PCIRST#. This register can be written only
once after PCIRST# deassertion.
Bits
Description
31:16
15:0
Subsystem ID (SSID)—R/WO. Write once field for sub-system ID.
Subsystem Vendor ID (SSVID)—R/WO. Write once field for holding the subsystem vendor ID.
3.4.1.10
CAP_PTR—Capabilities Pointer Register (D28,30: F0)
Offset:
34h
Default Value: 50h
Attribute:
Size:
RO
8 bits
Bits
Description
7:0
Capabilities Pointer (PTR). This field indicates that the pointer for the first entry in the
capabilities list is at 50h in PCI configuration space.
3.4.1.11
ABAR—Alternate Base Address Register (D28,30: F0)
Offset:
40–41h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
This register contains an alternate base address in the legacy APIC range. This range can co-exist
with the BAR Register range. This range is needed for operating systems that support the APIC
but do not yet support remapping the APIC anywhere in the 4 GB address space.
Bits
Description
15
14:12
11:8
7:4
3:0
I/OxAPIC Alternate Range Enable (EN). When set, the range FECXYZ00 to FECXYZFF is
enabled as an alternate access method to the I/OxAPIC registers. Bits ’XYZ’ are defined below.
0 = Disable (default)
1 = Enable
Reserved
Base Address [19:16] (XBAD). These bits determine the high order bits of the I/O APIC address
map. When a memory address is recognized by the P64H2, which matches FECXYZ00 or
FECXYZ10, the Intel® P64H2 will respond to the cycle and access the internal I/OxAPIC.
Base Address [15:12] (YBAD). These bits determine the low order bits of the I/OxAPIC address
map. When a memory address is recognized by the P64H2, which matches FECXYZ00 or
FECXYZ10, the P64H2 will respond to the cycle and access the internal I/OxAPIC.
Base Address [11:8] (ZBAD). These bits determine the low order bits of the I/OxAPIC address
map. When a memory address is recognized by the P64H2, which matches FECXYZ00 or
FECXYZ10, the P64H2 will respond to the cycle and access the internal I/OxAPIC.
Intel^® 82870P2 P64H2 Datasheet
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