82870P2P64H2 Datasheet, PDF (123/217 Pages) –

Functional Description
R
4.1.9.10
4.1.9.11
4.1.9.12
System Errors
PCI SERR# Pin Assertion
When PxSERR# is sampled asserted, the P64H2 sets the received system error bit in the secondary
status register. It generates the DO_SERR special cycle if:
• The SERR# Forward Enable bit is set in the Bridge Control Register, and
• The Primary SERR# Enable bit is set in the PD_CMD Register.
Other System Errors
The P64H2 also conditionally initiates the DO_SERR special cycle for any of the following
reasons:
• Parity error reported on target bus during write transactions
• Master timeout on delayed transaction if the Primary SERR# Enable bit is set and SERR# due
to Timeout Enable bit (bit 11 of offset 3E–3Fh) is set.
• The MAM bit (Master Abort Mode) is set in the Bridge Control Register and a posted write
from the hub interface results in a master abort on PCI, or a posted write from one PCI
interface results in a master abort on the other PCI interface. (No indication is given back on
the hub interface if a posted PCI write fails on the hub interface – the MCH must handle this
condition).
Intel^® 82870P2 P64H2 Datasheet
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