82870P2P64H2 Datasheet, PDF (115/217 Pages) –

Functional Description
R
4.1.5
4.1.6
Non-Posted
Delayed write forwarding is not used. It is only for I/O write transactions. Since the P64H2 does
not support I/O write transactions across a bridge, these cycles all result in a master abort. Note
that configuration cycles are not allowed to cross a bridge as indicated in the PCI-to-PCI Bridge
Architecture Specification, Revision 1.1.
Fast Back-to-Back
The P64H2 allows fast back-to-back write transactions on PCI.
Read Transactions
Prefetchable
Any memory read multiple command on PCI that are decoded by the P64H2 are prefetched on the
hub interface. Prefetching may be optionally disabled if bit 4 of the P64H2 Configuration Register
(offset 40–41h) is set. The P64H2 does not prefetch past a 4 KB page boundary.
Delayed
All memory read transactions are delayed read transactions. When the P64H2 accepts a delayed
read request, it samples the address, command, and address parity. This information is entered into
the delayed transaction queue. All I/O transactions will master abort.
Configuration Transactions
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus
as the initiator. A Type 0 configuration transaction is identified by the configuration command and
the lowest 2 bits of the address set to 00b.
Type 1-configuration transactions are issued when the intended target resides on another PCI bus,
or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is
identified by the configuration command and the lowest 2 address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWord address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For
single-function devices, this value is not decoded. Type 1 configuration transaction addresses also
include a 5-bit field designating the device number that identifies the device on the target PCI bus
that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to
which the transaction is targeted.
Intel^® 82870P2 P64H2 Datasheet
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