82870P2P64H2 Datasheet, PDF (83/217 Pages) –

Register Description
R
3.3.2 Memory Space Registers
This section provides the memory space registers for the hot plug controller. The MBAR Register
(PCI offset 10h) and MBARU Register (PCI offset 14h) provide the base address for the memory
space registers. The address offset listed in Table 17 are offset from this base address.
Table 17. Hot Plug Controller Memory Space Register Map
Address
Offset
00h
01h
02–03h
04–07h
08–0Bh
0C–0Fh
10–11h
13h
14–17h
28h
2Ch
2Dh
32–33h
Symbol
Register Name
GPT
SE
MCNF
LEDC
HMIC
HMIR
SIR
GPO
HMIN
SID
SIRE
SPE
EMR
General Purpose Timer
Slot Enable
Miscellaneous Configuration
LED Control
Hot Plug Interrupt Input and Clear
Hot Plug Interrupt Mask
Serial Input Register
General Purpose Output
Hot Plug Non-Interrupt Inputs
Slot ID
Switch Interrupt Redirect Enable
Slot Power Enable
Extended Hot Plug Miscellaneous
Default
00h
00h
00h
00h
00h
FFh
00h
00h
00h
00h
00h
00h
00h
Access
R/W
R/W
R/W, RO,
R/WC
R/W
R/WC
R/W
R/W, RO
R/W
RO
R/W
R/W
R/W
R/W
Intel^® 82870P2 P64H2 Datasheet
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