82870P2P64H2 Datasheet, PDF (72/217 Pages) –

Register Description
R
3.3.1.4
3.3.1.5
PCISTS—PCI Status Register (Device 31)
Offset:
06–07h
Default Value: 0230h
Attribute:
Size:
R/WC, RO
16 bits
This register reports the status of PCI events generated by the hot plug controller.
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
15
1 = Intel® P64H2 hot plug controller detected a data parity error.
Note: Software clears this bit by writing a 1 to it.
Signaled System Error (SSE)—R/WC.
0 = No SERR# generated.
14
1 = P64H2 hot plug controller generates SERR#.
Note: Software clears this bit by writing a 1 to it.
13 Received Master Abort (RMA)—RO. Hardwired to 0; Reserved.
12 Received Target Abort (RTA)—RO. Hardwired to 0; Reserved.
11 Signaled Target Abort (STA)—RO. Hardwired to 0; Reserved.
10:9
DEVSEL timing (DVT)—RO. Hardwired to 10; indicates that the hot plug controller responds in
medium decode time.
8
Data Parity Detected (DPD)—RO. Hardwired to 0; Reserved
7:6 Reserved
5
66 MHz Capable (C66)—RO. Hardwired to 1; controller is capable of operating at 66 MHz.
4
Capabilities List Exists (CLIST)—RO. Hardwired to 1; indicates that this device supports a
capabilities list. The pointer to the first item is located at offset 34h.
3:0 Reserved
RID—Revision ID Register (Device 31)
Offset:
08h
Default Value: 04h
Attribute:
Size:
Indicates the revision of the hot plug controller.
RO
8 bits
Bits
Description
Revision ID (RID). This filed indicates the stepping of the Intel® P64H2.
7:0 _{03h = B0 Stepping}
04h = B1 Stepping
72
Intel^® 82870P2 P64H2 Datasheet