82870P2P64H2 Datasheet, PDF (71/217 Pages) –

Register Description
R
3.3.1.1
3.3.1.2
3.3.1.3
VID—Vendor ID Register (Device 31)
Offset:
00–01h
Default Value: 8086h
Attribute:
Size:
RO
16 bits
Bits
Description
15:0 Vendor ID (VID): Indicates that Intel was the vendor of this controller.
DID—Device ID Register (Device 31)
Offset:
02–03h
Default Value: 1462h
Attribute:
Size:
RO
16 bits
Bits
Description
15:0 Device Identifier (DID): Indicates the device number of this controller.
PCICMD—PCI Command Register (Device 31)
Offset:
04–05h
Default Value: 00h
Attribute:
Size:
R/W, RO
16 bits
Bits
Description
15:10
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back-to-Back Enable (FBE)—RO. Hardwired to 0. Reserved.
PxSERR# Enable (SEE)—R/W.:
0 = Disable. (Default)
1 = Enable. Intel® P64H2 hot plug controller is allowed to generate PxSERR# on any event that is
enabled for PxSERR# generation.
Wait Cycle Enable (WCC)—RO. Reserved.
Parity Error Response Enable (PEE)—R/W.
0 = Disable. (Default)
1 = Enable. P64H2 hot plug controller will generate PxSERR# when a data parity error is detected
and SEE (bit 8) is set.
VGA Palette Snooping Enable (VGA)—RO. Hardwired to 0. Reserved.
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. Reserved.
Special Cycle Enable (SCE)—RO. Hardwired to 0. Reserved.
Bus Master Enable (BME)—R/W.: Hardwired to 0. Reserved.
Memory Space Enable: (MSE)—R/W.
0 = Disable. (Default)
1 = Enable. Memory space registers are accessible through the memory address range set by
MBAR and MBARU.
IO Space Enable: (IOSE)—RO. Hardwired to 0. Reserved.
Intel^® 82870P2 P64H2 Datasheet
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